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US 11,600,327 B2Granted
Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation
AssigneeKioxia Corporation
InventorsKenrou Kikuchi, Yasuhiro Shimura
Life of this patent
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Abstract
A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.
Claims9
A semiconductor memory device comprising:
- a first memory string including a plurality of first memory cell transistors connected to each other in series;
- a plurality of word lines connected to the plurality of first memory cell transistors, respectively;
- a first select transistor connected to one end of the first memory string;
- a first gate line connected to the first select transistor;
- a second select transistor connected to another end of the first memory string;
- a second gate line connected to the second select transistor;
- a bit line connected to the first select transistor;
- a source line connected to the second select transistor;
- and
- a control circuit configured to execute a plurality of write operations for writing data to the plurality of first memory cell transistors and a program operation including a plurality of verify operations, wherein
- when,
- among the plurality of first memory cell transistors, a memory cell transistor that is a target to write data is a first write target transistor,
- among the plurality of word lines, a word line to be connected to the first write target transistor is a select word line, and
- among the plurality of word lines, word lines other than the select word line are non-select word lines,
- at completion of the program operation to write data to the first write target transistor:
- a voltage to turn on the first select transistor is applied to the first gate line,
- a voltage to turn on the second select transistor is applied to the second gate line, and
- a predetermined first voltage higher than a ground voltage is applied to the select word line and the non-select word lines;
- and
- subsequent to the completion of the program operation:
- a voltage to turn off the first select transistor is applied to the first gate line,
- a voltage to turn off the second select transistor is applied to the second gate line, and
- a predetermined second voltage higher than the ground voltage is applied to the select word line and the non-select word lines, wherein the voltage applied to the select word line and the non-select word lines is equal to or greater than the second voltage from a time of the completion of the program operation to a time subsequent to the completion of the program operation.
20 more elements
A semiconductor memory device comprising:
- a first memory string including a plurality of first memory cell transistors connected to each other in series;
- a plurality of word lines connected to the plurality of first memory cell transistors, respectively;
- a first select transistor connected to one end of the first memory string;
- a first gate line connected to the first select transistor;
- a second select transistor connected to another end of the first memory string;
- a second gate line connected to the second select transistor;
- a bit line connected to the first select transistor;
- a source line connected to the second select transistor;
- and
- a control circuit configured to execute a plurality of write operations for writing data to the plurality of first memory cell transistors and a program operation including a plurality of verify operations, wherein
- when,
- among the plurality of first memory cell transistors, a memory cell transistor that is a target to write data is a first write target transistor,
- among the plurality of word lines, a word line to be connected to the first write target transistor is a select word line,
- among the plurality of word lines, word lines on a side of the bit line with respect to the select word line are first non-select word lines, and
- among the plurality of word lines, word lines on a side of the source line with respect to the select word line are second non-select word lines,
- at completion of the program operation to write data to the first write target transistor:
- a voltage to turn on the first select transistor is applied to the first gate line,
- a voltage to turn on the second select transistor is applied to the second gate line, and
- a predetermined first voltage higher than a ground voltage is applied to the select word line and the first non-select word lines and a second voltage higher than the ground voltage but lower than the first voltage is applied to the second non-select word lines;
- and
- subsequent to the completion of the program operation:
- a voltage to turn off the first select transistor is applied to the first gate line,
- a voltage to turn off the second select transistor is applied to the second gate line, and
- a predetermined third voltage higher than the ground voltage is applied to the select word line and the first non-select word lines, wherein a fourth voltage higher than the ground voltage but lower than the third voltage is applied to the second non-select word lines.
21 more elements
Dependencies are inferred from the claim text.