Non volatile resistive memory logic device
AssigneeInternational Business Machines Corporation
InventorsHsueh-Chung Chen, Mary Claire Silvestre, Soon-Cheon Seo, Chi-Chun Liu, Fee Li Lie, Chih-Chao Yang, Yann Mignot, Theodorus E. Standaert
Life of this patent
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Abstract
A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.
Claims19
A resistance switching random access memory (RAM) NAND device comprising:
- a first resistive RAM (RRAM) cell and a first input node electrically connected to the first RRAM cell;
- a second RRAM cell and a second input node electrically connected to the second RRAM cell;
- and
- a shared output node electrically connected to both the first RRAM cell and the second RRAM cell.
A resistance switching random access memory (RAM) NOR device comprising:
- a first resistive RAM (RRAM) cell;
- a second RRAM cell;
- a shared input node electrically connected to both the first RRAM cell and to the second RRAM cell, the shared input node comprising a first input and a second input;
- and
- a shared output node electrically connected to both the first RRAM cell and to the second RRAM cell.
A resistance switching random access memory (RAM) NAND device comprising:
- a first magnetoresistive RAM (MRAM) cell and a first input node electrically connected to the first MRAM cell;
- a second MRAM cell and a second input node electrically connected to the second MRAM cell;
- and
- a shared output node electrically connected to both the first MRAM cell and the second MRAM cell.
Dependencies are inferred from the claim text.