Semiconductor memory device and method of operating the same

A semiconductor memory device comprising:

• a memory block including a plurality of drain select transistors, and a plurality of memory cells programmable to first to n-th program states;
• a voltage generator configured to generate a program voltage and a select line voltage to apply to the memory block during a plurality of program operations corresponding to the respective first to n-th program states;
• a read and write circuit configured to apply a program permission voltage or a program inhibition voltage to bit lines of the memory block based on program data;
• and
• control logic configured to control the voltage generator and the read and write circuit to sequentially perform the plurality of program operations,
• wherein the control logic controls the voltage generator to:
• generate the select line voltage as a first select line voltage during a program operation corresponding to the first program state to a specific program state, and
• generate the select line voltage as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a program operation corresponding to at least one program state next to the specific program state, and
• wherein each of the first select line voltage and the second select line voltage is greater than a sum of the program permission voltage and a highest threshold voltage of the plurality of drain select transistors, and is less than a sum of the program inhibition voltage and a lowest threshold voltage of the plurality of drain select transistors.

A method of operating a semiconductor memory device, the method comprising:

• setting a drain select line voltage, applied to a drain select line coupled to a plurality of drain select transistors included in the semiconductor memory device, to a first drain select line voltage;
• sequentially performing a plurality of first program loops corresponding to first to specific program states among first to n-th program states while a program permission voltage or a program inhibition voltage is applied to each of bit lines coupled to memory cells included in the semiconductor memory device;
• setting the drain select line voltage to a second drain select line voltage for which a potential is lower than a potential of the first drain select line voltage when a program operation corresponding to the specific program state is completed;
• and
• sequentially performing a plurality of second program loops corresponding to a program state next to the specific program state,
• wherein each of the first drain select line voltage and the second drain select line voltage is greater than a sum of the program permission voltage and a highest threshold voltage of the plurality of drain select transistors, and is less than a sum of the program inhibition voltage and a lowest threshold voltage of the plurality of drain select transistors.