Perpectual digital perceptron
AssigneeFlashsilicon Incorporation
InventorLee Wang
Life of this patent
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Abstract
An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.
Claims17
A digital perceptron device, comprising:
- a first read-only-memory (ROM) array comprising m rows by n columns of first memory cells for parallel comparing a n-bit input symbol with a number m of n-bit content symbols hardwired in the m rows of first memory cells, wherein each row of the first memory cells generates an indication signal indicative of whether the n-bit input symbol matches its hardwired n-bit content symbol;
- a detection circuit for respectively applying a number m of switching signals to a number m of wordlines of a second ROM array in response to a number m of indication signals;
- and
- the second ROM array comprising m rows by q columns of second memory cells, wherein a number m of q-bit response symbols are respectively hardwired in the m rows of second memory cells;
- wherein while receiving an activated switching signal, a row of second memory cells is switched on to output its hardwired q-bit response symbol as a q-bit output symbol;
- and
- wherein the q-bit output symbol is autonomously processed with the n-bit input symbol according to the number m of n-bit content symbols and the number m of q-bit response symbols.
A method for operating a digital perceptron device comprising a first read-only-memory (ROM) array and a second ROM array, the method comprising:
- parallel comparing an n-bit input symbol with a number m of n-bit content symbols hardwired in the first ROM array comprising m rows by n columns of first memory cells so that each row of first memory cells generates an indication signal indicative of whether the n-bit input symbol matches its hardwired n-bit content symbol;
- respectively applying a number m of switching signals to a number m of wordlines in the second ROM array comprising m rows by q columns of second memory cells according to a number m of indication signals, wherein a number m of q-bit response symbols are hardwired in the m rows of second memory cells;
- switching on a row of second memory cells to output its hardwired q-bit response symbol as a q-bit output symbol in response to a received activated switching signal;
- and
- switching off a row of second memory cells in response to a received de-activated switching signal;
- wherein the q-bit output symbol is autonomously processed with the n-bit input symbol according to the number m of n-bit content symbols and the number m of q-bit response symbols.
Dependencies are inferred from the claim text.