Memory system capable of performing a bit partitioning process and an internal computation process
AssigneeNational Cheng Kung University
InventorsLih-Yih Chiou, Yu-Wei Lin, Wei-Shuo Ling
Life of this patent
Estimating the term…
Abstract
A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.
Claims10
A memory system comprising:
- a plurality of first memory units, each first memory unit of the plurality of first memory units comprising:
- a second memory unit;
- a first transistor coupled to the second memory unit;
- and
- a second transistor coupled to the second memory unit and the first transistor;
- a plurality of read word lines, each read word line of the plurality of read word lines being coupled to a plurality of first transistors disposed along a corresponding row;
- and
- a plurality of read bit lines, each read bit line of the plurality of read bit lines being coupled to a plurality of second transistors disposed along a corresponding column;
- wherein a current of the each read bit line is generated by performing a linear combination on a plurality of currents of the plurality of read word lines.
Dependencies are inferred from the claim text.