Memory array with reduced leakage current

An apparatus for reading a bit of a memory array, the apparatus comprising:

• a current source configured to generate a read current;
• a bitcell column comprising a plurality of bitcell elements arranged in parallel, each bitcell element of the plurality of bitcell elements comprising a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline, the series string comprising a switching element coupled in series with a resistive element;
• voltage enhancement circuitry configured to couple the bitline to a reference node;
• control circuitry configured to:
• in response to a read request for a bitcell element of the plurality of bitcell elements, couple a current source to the bitcell column such that the read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node;
• and
• determine a state for the bitcell element based on a voltage between the source line and the reference node;
• and
• wherein the voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

A method of operating a memory device comprising:

• receiving a read request for a bitcell element of a plurality of bitcell elements, wherein the plurality of bitcell elements are arranged in parallel to form a bitcell column, each bitcell element of the plurality of bitcell elements comprising a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline, the series string comprising a switching element coupled in series with a resistive element;
• in response to the read request, coupling a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and voltage enhancement circuitry, to a reference node, wherein the voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node;
• and
• determining a state for the bitcell element based on a voltage between the source line and the reference node.