Memory controller and method of operating the same
AssigneeSK hynix Inc.
InventorsHyun Sub Kim, Ie Ryung Park, Dong Sop Lee
Life of this patent
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Abstract
A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.
Claims20
A storage device comprising:
- a plurality of memory devices;
- and
- a memory controller coupled with the plurality of memory devices through a plurality of channels, respectively, and configured to control the plurality of memory devices,
- wherein, when a selected memory device among the plurality of memory devices starts an operation, the memory controller generates a clock signal based on an idle time interval of at least one unselected memory device among the plurality of memory devices and outputs the generated clock signal to the selected memory device.
A storage device comprising:
- a plurality of memory devices;
- and
- a memory controller coupled with the plurality of memory devices through a channel and configured to control the plurality of memory devices,
- wherein, when a selected memory device among the plurality of memory devices starts an operation, the memory controller generates a clock signal based on an idle time interval of at least one unselected memory device among the plurality of memory devices and outputs the generated clock signal to the selected memory device.
Dependencies are inferred from the claim text.