US 11,600,309 B2 · 3D memory with 3D sense amplifier

Abstract

Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

Claims154

Dependent claims

A 3D inverter, comprising:

a first vertical MOSFET;
a second vertical MOSFET;
an interconnect line disposed below said 3D inverter;
a metal line disposed above said 3D inverter;
and wherein:
each of said first vertical MOSFET and said second vertical MOSFET comprises a gate, a source region, and a drain region;
said drain region of said first vertical MOSFET is coupled to said source region of said second vertical MOSFET and to an output of said 3D inverter;
said source region of said first vertical MOSFET is coupled to a first common node;
said drain region of said second vertical MOSFET is coupled to a second common node;
said gate of said first vertical MOSFET is coupled to an input of said 3D inverter;
and
said gate of said second vertical MOSFET is coupled to a third common node.

9 more elements

A 3D sense amplifier for a 3D memory, comprising:

a first 3D inverter with an input and an output;
a second 3D inverter with an input and an output;
a first bit line carrying a first signal;
a second bit line carrying a second signal;
and wherein:
each of said first 3D inverter and said second 3D inverter comprises:
a first vertical MOSFET with a gate, a source region, and a drain region;
and
a second vertical MOSFET with a gate, a source region, and a drain region;
said first bit line is coupled to said input of said first 3D inverter and to said output of said second 3D inverter;
said second bit line is coupled to said input of said second 3D inverter and to said output of said first 3D inverter;
said input of said first 3D inverter is coupled to said gate of first vertical MOSFET of said first 3D inverter;
said input of said second 3D inverter is coupled to said gate of first vertical MOSFET of said second 3D inverter;
said source region of said first vertical MOSFET of said first 3D inverter and said source region of said first vertical MOSFET of said second 3D inverter are coupled to a first common node;
said drain region of said second vertical MOSFET of said first 3D inverter and said drain region of said second vertical MOSFET of said second 3D inverter are coupled to a second common node;
said gate of said second vertical MOSFET of said first 3D inverter and said gate of said second vertical MOSFET of said second 3D inverter are coupled to a third common node;
said drain region of said first vertical MOSFET of said first 3D inverter and said source region of said second vertical MOSFET of said first 3D inverter are coupled to said output of said first 3D inverter;
said drain region of said first vertical MOSFET of said second 3D inverter and said source region of said second vertical MOSFET of said second 3D inverter are coupled to said output of said second 3D inverter;
and
said first signal is configured to respond to charges stored in a cell of said 3D memory during a second phase of a memory operation of said 3D memory.

17 more elements

A 3D sense amplifier for a 3D memory, comprising:

a first 3D inverter with an input and an output;
a second 3D inverter with an input and an output;
a first bit line carrying a first signal;
a second bit line carrying a second signal;
and wherein:
each of said first 3D inverter and said second 3D inverter comprises:
a vertical n-MOSFET with a gate, a source region, and a drain region;
and
a p-MOSFET with a gate, a source region, and a drain region;
said first bit line is coupled to said input of said first 3D inverter and to said output of said second 3D inverter;
said second bit line is coupled to said input of said second 3D inverter and to said output of said first 3D inverter;
said gate of said vertical n-MOSFET of said first 3D inverter and said gate of said p-MOSFET of said first 3D inverter are coupled to said input of said first 3D inverter;
said gate of said vertical n-MOSFET of said second 3D inverter and said gate of said p-MOSFET of said second 3D inverter are coupled to said input of said second 3D inverter;
said drain region of said vertical n-MOSFET of said first 3D inverter and said drain region of said p-MOSFET of said first 3D inverter are coupled to said output of said first 3D inverter;
said drain region of said vertical n-MOSFET of said second 3D inverter and said drain region of said p-MOSFET of said second 3D inverter are coupled to said output of said second 3D inverter;
said source region of said vertical n-MOSFET of said first 3D inverter and said source region of said vertical n-MOSFET of said second 3D inverter are coupled to a first common node;
said source region of said p-MOSFET of said first 3D inverter and said source region of said p-MOSFET of said second 3D inverter are coupled to a second common node;
and
said first signal is configured to respond to charges stored in a cell of said 3D memory during a second phase of a memory operation of said 3D memory.

16 more elements

A 3D sense amplifier for a 3D memory, comprising:

a first input;
a second input;
a first vertical n-MOSFET with a gate, a source region, and a drain region;
a second vertical n-MOSFET with a gate, a source region, and a drain region;
a first vertical p-MOSFET with a gate, a source region, and a drain region;
a second vertical p-MOSFET with a gate, a source region, and a drain region;
a first bit line carrying a first bit-line signal from said 3D memory;
a second bit line carrying a second bit-line signal from said 3D memory;
and wherein:
said first bit line is coupled to said first input of said 3D sense amplifier;
said second bit line is coupled to said second input of said 3D sense amplifier;
said first input of said 3D sense amplifier is coupled to said drain region of said first vertical n-MOSFET, said drain region of said first vertical p-MOSFET, said gate of said second vertical n-MOSFET, and said gate of said second vertical p-MOSFET;
said second input of said 3D sense amplifier is coupled to said drain region of said second vertical n-MOSFET, said drain region of said second vertical p-MOSFET, said gate of said first vertical n-MOSFET, and said gate of said first vertical p-MOSFET;
said source region of said first vertical n-MOSFET and said source region of said second vertical n-MOSFET are coupled to a first common node;
said source region of said first vertical p-MOSFET and said source region of said second vertical p-MOSFET are coupled to a second common node;
and
said first bit-line signal is configured to respond to charges stored in a cell of said 3D memory along said first bit line during a second phase of a memory operation of said 3D memory.

14 more elements

Dependencies are inferred from the claim text.

3D memory with 3D sense amplifier

Life of this patent

3D memory with 3D sense amplifier

Life of this patent

Abstract

Claims154