Semiconductor memory device, processing system including the same and power control circuit for the same
AssigneeSK hynix Inc.
InventorChang Hyun Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device may include a plurality of memory cells wherein identifiers may be provided to the memory cells. The semiconductor memory device may include a first circuit, a second circuit and a power control circuit. The first circuit may include a first power terminal and a second power terminal. The second circuit may include a third terminal and a fourth terminal. The power control circuit may be configured to apply a first power voltage or a ground voltage to the first power terminal and to apply the ground voltage to the second power terminal based on the identifiers.
Claims13
A semiconductor memory device including a plurality of memory cells to which identifiers are assigned, respectively, the semiconductor memory device comprising:
- a first circuit including a first power terminal and a second power terminal;
- a second circuit including a third power terminal and a fourth power terminal;
- and
- a power control circuit configured to apply a first power voltage or a ground voltage to the first power terminal and the ground voltage to the second power terminal based on the identifiers.
A processing system comprising:
- a base die;
- and
- at least one core die stacked on the base die and coupled to the base die through a connection via, the core die including a plurality of memory cells to which identifiers are assigned, respectively,
- wherein the core die comprises:
- a first circuit including a first power terminal and a second power terminal;
- a second circuit including a third power terminal and a fourth power terminal;
- and
- a power control circuit configured to apply a first power voltage or a ground voltage to the first power terminal and the ground voltage to the second power terminal based on the identifiers.
A processing system comprising:
- a base die;
- and
- a stacked structure stacked on the base die and coupled to the base die through a connection via, the stacked structure including a plurality of memory cells to which identifiers are assigned, respectively,
- wherein the stacked structure comprises:
- a master core die directly stacked on the base die, the master core die including a first circuit and a second circuit, a first power terminal of the first circuit included in the master core die configured to receive a first power voltage, a second power terminal of the first circuit included in the master core die configured to receive a ground voltage, a third power terminal of the second circuit included in the master core die configured to receive a second power voltage and a fourth power terminal of the second circuit included in the master core die configured to receive the ground voltage;
- and
- at least one slave core die stacked on or over the master core die, the slave core die including a first circuit and a second circuit, a first power terminal of the first circuit included in the slave core die configured to receive the ground voltage, a second power terminal of the first circuit included in the slave core die configured to receive the ground voltage, a third power terminal of the second circuit included in the slave core die configured to receive the second power voltage and a fourth power terminal of the second circuit included in the slave core die configured to receive the ground voltage.
Dependencies are inferred from the claim text.