Memory circuit architecture

A method of operating a semiconductor device, the method comprising:

• performing an input or output operation on a memory circuit, including receiving an enable signal directed toward a first quadrant of a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component;
• wherein the first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit;
• wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical;
• wherein performing the input or output operation on the memory circuit includes performing pre-decoding at the bank control component and activating word line drivers in a row decoder according to the pre-decoding.

A system on chip (SOC) comprising:

• a random-access memory (RAM) device comprising a plurality of quadrants arranged around corners of a rectangular shape of the RAM device;
• wherein a first quadrant of the plurality of quadrants is defined by a first boundary that encloses portions of two perpendicular edges of the RAM device;
• wherein a second quadrant of the plurality of quadrants is horizontal axis symmetrical with respect to the first quadrant;
• and
• wherein a third quadrant of the plurality of quadrants is vertical axis symmetrical with respect to the first quadrant.

A semiconductor device comprising:

• a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component;
• wherein a first quadrant of the plurality of quadrants includes a first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit;
• and
• wherein a second quadrant of the plurality of quadrants includes a second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.