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US 11,600,213 B2Granted
Level shifter, gate driving circuit, and display device
AssigneeLG Display Co., Ltd.
InventorsSujin Hwang, MiYoung Son, EungKyu Kim, HongJae Shin, MinKyu Chang
Life of this patent
Estimating the term…
Abstract
A display device includes a level shifter and a gate driving circuit that can reduce differences in characteristics among gate signals to improve image quality by controlling a signal waveform of a first clock signal of the m number of clock signals different from a signal waveform of an m-th clock signal when m number of gate signals is output by using m number of clock signals.
Claims23
A display device comprising:
- a substrate;
- m number of gate lines disposed over the substrate where m is a natural number of 2 or more;
- and
- a gate driving circuit disposed over the substrate and configured to supply m number of gate signals based on m number of clock signals to the m number of gate lines,
- wherein the gate driving circuit comprises m number of output buffer circuits configured to output the m number of gate signals based on the m number of clock signals, and a control circuit configured to control the m number of output buffer circuits,
- wherein each of the m number of output buffer circuits comprises a pull-up transistor and a pull-down transistor, and a point at which the pull-up transistor and the pull-down transistor are connected is electrically connected with a corresponding gate line among the m number of gate lines,
- wherein all gate nodes of the pull-up transistors included in the m number of output buffer circuits are electrically connected with one another, and all gate nodes of the pull-down transistors included in the m number of output buffer circuits are electrically connected with one another, and
- wherein a signal waveform of at least one of the m number of clock signals is different from at least one signal waveforms of at least one other clock signals of the m number of clock signals.
5 more elements
A gate driving circuit comprising:
- m number of output buffer circuits configured to output m number of gate signals based on m number of clock signals where m is a natural number of 2 or more;
- and
- a control circuit configured to control the m output buffer circuits,
- wherein each of the m number of output buffer circuits comprises a pull-up transistor and a pull-down transistor and a point at which the pull-up transistor and the pull-down transistor are connected is electrically connected with a corresponding gate line of the m number of gate lines,
- wherein all gate nodes of the pull-up transistors in the m number of output buffer circuits are electrically connected with one another, and all gate nodes of the pull-down transistors in the m number of output buffer circuits are electrically connected with one another, and
- wherein a signal waveform of at least one of the m number of clock signals is different from at least one of signal waveforms of at least one of other clock signals.
3 more elements
A level shifter comprising:
- m number of clock output buffers configured to output m number of clock signals including first to m-th clock signals where m is a natural number of 2 or more,
- wherein each of the first and second clock signals among the first to m-th clock signals has a high level voltage duration partially overlap with each other, and
- wherein the first clock signal has a signal waveform different from at least one signal waveforms of at least one other clock signals among the m number of clock signals,
- wherein a falling length of the first clock signal of them number of clock signals is greater than a falling length of the m-th clock signal.
1 more element
A display device comprising:
- m number of gate lines disposed over a substrate where m is a natural number of 2 or more;
- a gate driving circuit disposed over the substrate and configured to supply m number of gate signals based on m number of clock signals to the m number of gate lines;
- a level shifter configured to supply the m number of clock signals to the gate driving circuit and including m number of clock output buffers configured to output the m number of clock signals including first to m-th clock signals;
- and
- a printed circuit board where the level shifter is disposed,
- wherein a falling length of the first clock signal of them number of clock signals is greater than a falling length of the m-th clock signal.
3 more elements
Dependencies are inferred from the claim text.