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AssigneeInternational Business Machines Corporation
InventorsPradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V Swaminathan, Augusto Vega, Swagath Venkataramani
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An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.
A computer-implemented N modular redundancy (N-MR) method for neural networks, the method comprising:
An N modular redundancy (N-MR) system for neural networks, said system comprising:
A computer program product for N modular redundancy (N-MR) for neural networks, the computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform:
Dependencies are inferred from the claim text.
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Neural networks: learning methods
Error detection or correction of the data by redundancy in operations: in neural networks
Architecture, e.g. interconnection topology: combinations of networks
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
About 13 years 8 months of term left · ends 13 Jun 2040 (estimated)
The present invention relates generally to an N modular redundancy method (where N is an integer greater than 0), and more particularly, but not by way of limitation, to a system, method, and computer program product for the use of small neural network checkers and selective N modular redundancy (N-MR) applied only to critical computations.
Conventionally, N Modular Redundancy (N-MR) is a fault detection/correction technique that can be applied to generic systems, but also to neural networks (eg., both convolutional and recurrent). N-MR provides a way to improve the resilience of computed systems to run-time faults. N-MR is applied at a level of a complete neural network and not at the level of individual computation.
However, while N-MR can replicate graph(s) (e.g., directed acyclic graphs) to check accuracy, N-MR is often prohibitively expensive as it requires replicating computation by a factor of N either temporally (e.g., through serially repeating computation N times) or spatially (through N redundant hardware units operating in parallel).
Aspects of the invention will be better understood from the following detailed description of the exemplary embodiments of the invention with reference to the drawings, in which:
FIG. 1 exemplarily shows a high-level flow chart for an N modular redundancy method 100 according to an embodiment of the present invention;
FIG. 2 exemplarily shows a first embodiment of checker neural networks;
The invention will now be described with reference to FIGS. 1-7, in which like reference numerals refer to like parts throughout. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for clarity,
By way of introduction of the example depicted in FIG. 1, an embodiment of an N modular redundancy method 100 according to the present invention can include various steps for reducing the cost of N modular redundancy(N-MR) for neural networks through selective replication.
By way of introduction of the example depicted in FIG. 5, one or more computers of a computer system 12 according to an embodiment of the present invention can include a memory 28 having instructions stored in a storage system to perform the steps of FIG. 1.