Self-powered analog computing architecture with energy monitoring to enable machine-learning vision at the edge
AssigneeNortheastern University
InventorAatmesh Shrivastava
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Abstract
An analog computing method includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.
Claims12
An analog computing method, comprising:
- (a) generating a biasing current (IWi) using a constant gm bias circuit operating in a subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, said circuit including a switched capacitor resistor;
- and
- (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi), wherein the differential amplifier multiplication circuit comprises a pair of transistors coupled at their sources for receiving the biasing current, wherein the input voltage is applied to the gates of the transistors, and wherein (i) the drains of the transistors are coupled to a capacitor across which the analog voltage output of the amplifier multiplication circuit is sampled or (ii) the drains of the transistors are each coupled to a load capacitor and the analog voltage output of the amplifier multiplication circuit is sampled across the drains.
An analog computing circuit, comprising:
- a constant gm bias circuit operating in a subthreshold region for ultra-low power consumption for generating a biasing current (IWi), wherein gm in the constant gm bias circuit is generated by PMOS or NMOS transistors, said constant gm bias circuit including a switched capacitor resistor;
- and
- a differential amplifier multiplication circuit coupled to the constant gm bias circuit for receiving the biasing current and an input voltage and multiplying the biasing current by the input voltage to generate an analog voltage output (VOi), wherein the differential amplifier multiplication circuit comprises a pair of transistors coupled at their sources for receiving the biasing current, wherein the input voltage is applied to the gates of the transistors, and wherein (i) the drains of the transistors are coupled to a capacitor across which the analog voltage output of the amplifier multiplication circuit is sampled or (ii) the drains of the transistors are each coupled to a load capacitor and the analog voltage output of the amplifier multiplication circuit is sampled across the drains.
Dependencies are inferred from the claim text.