Processor in memory supporting binary convolution operation and method of operating the same

An artificial neural network device comprising:

• an operation part configured to perform an artificial neural network operation on an input feature map;
• and
• a classification part configured to perform a classifying operation on the input feature map based on the artificial neural network operation of the operation part, the operation part comprising:
• an XNOR operation circuit configured to perform an XNOR operation on the input feature map and a filter;
• and
• a binarizing circuit configured to perform a binarization operation based on the result of the XNOR operation of the XNOR operation circuit, and output data of the output feature map based on a comparison result of discharge rates,
• wherein the discharge rates comprise a discharge rate of a match line connected to a memory cell array and a discharge rate of a reference match line.

A method of operating an artificial neural network device, comprising:

• programming data of an input feature map in a memory cell array;
• precharging at least one match line among a plurality of match lines connected to the memory cell array;
• providing weight data of a filter through at least one source line among a plurality of source lines connected to the memory cell array;
• performing an evaluation operation on the at least one match line based on the data stored in the memory cell array and the weight data of the filter;
• and
• outputting data of an output feature map based on a comparison result of a discharge rate of the at least one match line and a discharge rate of a reference match line.