US 11,599,679 B2Granted

Electromagnetic and power noise injection for hardware operation concealment

AssigneeArm Limited

InventorsBrendan James Moran, Matthias Lothar Boettcher

Life of this patent

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Abstract

A method of operation concealment for a cryptographic system includes randomly selecting which one of at least two cryptographic operation blocks receives a key to apply a valid operation to data and outputs a result that is used for subsequent operations. Noise can be added by operating the other of the at least two cryptographic operation blocks using a modified key. The modified key can be generated by mixing the key with a block-unique-identifier, a device secret, a slowly adjusting output of a counter, or a combination thereof. In some cases, noise can be added to a cryptographic system by transforming input data of the other cryptographic operation block(s) by mixing the input data with the block-unique-identifier, device secret, counter output, or a combination thereof. A cryptographic system with operation concealment can further include a distributed (across a chip) or interweaved arrangement of subblocks of the cryptographic operation blocks.

Claims18

Dependent claims

A system comprising:

at least two cryptographic operation blocks;
circuitry coupled to the at least two cryptographic operation blocks that route inputs and outputs between the at least two cryptographic operation blocks for subsequent computations wherein the circuitry comprises selection circuitry and a pseudorandom sequence generator (PRSG) that is coupled to the selection circuitry to control the selection circuitry;
a first block pad for outputting a first block-unique-identifier;
a second block pad for outputting a second block-unique-identifier;
a first combiner coupled to the first block pad, a key output, and the selection circuitry for mixing the first block-unique-identifier with a key and outputting a first modified key to the selection circuitry, wherein the selection circuitry selects whether the key or the first modified key is output to a first cryptographic operation block of the at least two cryptographic operation blocks under control of the PRSG;
and
a second combiner coupled to the second block pad, the key output, and the selection circuitry for mixing the second block-unique-identifier with the key and outputting a second modified key to the selection circuitry, wherein the selection circuitry selects whether the key or the second modified key is output to a second cryptographic operation block of the at least two cryptographic operation blocks under control of the PRSG.

4 more elements

A system comprising:

at least two cryptographic operation blocks;
circuitry coupled to the at least two cryptographic operation blocks that route inputs and outputs between the at least two cryptographic operation blocks for subsequent computations, wherein the circuitry comprises selection circuitry and a pseudorandom sequence generator (PRSG) that is coupled to the selection circuitry to control the selection circuitry;
a device secret output for outputting a device secret;
and
a combiner coupled to the device secret output, a key output, and the selection circuitry for mixing the device secret with a key from the key output and outputting a modified key to the selection circuitry, wherein the selection circuitry selects whether the key or the modified key is output to each of the at least two cryptographic operation blocks under control of the PRSG.

2 more elements

A system comprising:

at least two cryptographic operation blocks;
circuitry coupled to the at least two cryptographic operation blocks that route inputs and outputs between the at least two cryptographic operation blocks for subsequent computations, wherein the circuitry comprises selection circuitry and a pseudorandom sequence generator (PRSG) that is coupled to the selection circuitry to control the selection circuitry;
a first block pad for outputting a first block-unique-identifier;
a second block pad for outputting a second block-unique-identifier;
a device secret output for outputting a device secret;
a counter;
and
one or more combiners coupled to a key output, the counter, the device secret output, the first block pad, and the second block pad to derive a corresponding output, including a modified key,
wherein the selection circuitry is coupled to receive the modified key and the key output and select whether a key from the key output or the modified key is output to a first cryptographic operation block and a second cryptographic operation block of the at least two cryptographic operation blocks under control of the PRSG.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/908,853Filed 23 Jun 2020
Published: US 2021/0397747 A123 Dec 2021
Granted: 7 Mar 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 21/72
To assure secure computing or processing of information: in cryptographic circuits
H04L 9/002
Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols: countermeasures against…
G06F 21/602
Protecting data: providing cryptographic facilities or services
H04L 9/003
Countermeasures against attacks on cryptographic mechanisms: for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]