Computing in memory cell

A computing in memory cell, comprising:

• a memory cell circuit;
• a first semiconductor element having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first semiconductor element is adapted to be coupled to a first computing bit-line, and the control terminal of the first semiconductor element is adapted to be coupled to a first computing word-line;
• a second semiconductor element having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit, and the first terminal of the second semiconductor element is coupled to the second terminal of the first semiconductor element;
• and
• a third semiconductor element configured to provide a first weight resistance corresponding to a first weight, wherein a first terminal of the third semiconductor element is coupled to the second terminal of the second semiconductor element, a second terminal of the third semiconductor element is adapted to be coupled to a second computing bit-line, and a control terminal of the third semiconductor element is adapted to receive a first bias voltage corresponding to the first weight.