Device with data processing engine array that enables partial reconfiguration

A method for operating a device, the method comprising:

• operating a first kernel loaded on a first subset of an array of data processing engines (DPEs), each DPE of the array of DPEs comprising a core and a configuration memory space, the array of DPEs comprising a stream network and a memory mapped network, the stream network being configurable to route application data between DPEs of the array of DPEs;
• without modifying operation of the first kernel on the first subset of the array of DPEs, configuring a second subset of the array of DPEs to implement a second kernel, configuring the second subset of the array of DPEs comprising:
• routing memory mapped transactions via the memory mapped network, based on addresses contained in the respective memory mapped transactions, to the second subset of the array of DPEs;
• and
• writing configuration data of the respective memory mapped transactions to respective configuration memory spaces of DPEs of the second subset of the array of DPEs based on the addresses contained in the respective memory mapped transactions;
• and
• operating both the first kernel loaded on the first subset of the array of DPEs and the second kernel loaded on the second subset of the array of DPEs after configuring the second subset of the array of DPEs to implement the second kernel.

A device comprising:

• an array of data processing engines (DPEs), each DPE of the array of DPEs comprising a core, program memory, configuration registers, a memory mapped switch, and a stream switch, wherein:
• the program memory is configured to store executable program code that is executable by the core of the respective DPE;
• the configuration registers are configured to store interconnect data that configures the stream switch of the respective DPE for routing communications via the stream switch of the respective DPE;
• the memory mapped switch of the respective DPE is configured to route memory mapped transactions based on addresses contained in the respective memory mapped transactions;
• the memory mapped switches of the array of DPEs are communicatively coupled together to form a memory mapped network;
• and
• the stream switches of the array of DPEs are communicatively coupled together to form a stream network;
• the program memory and the configuration registers of each DPE of the array of DPEs are independently writeable based on configuration data contained in a memory mapped transaction received at the respective DPE via the memory mapped network;
• and
• the array of DPEs enabling, without modifying operation of a first kernel loaded on a first subset of the array of DPEs, reconfiguration of a second subset of the array of DPEs by memory mapped transactions through the memory mapped network.