High performance interconnect

An apparatus comprising:

• a retimer to extend a physical length of a link, wherein the link is to couple a first device to a second device, and the retimer is to be positioned between the first device and second device on the link, wherein the link is compliant with a PCIe-based protocol, and the retimer comprises protocol circuitry to:
• receive a first TS2 training sequence sent by the first device on a first link segment of the link, wherein the first link segment connects the first device to the retimer, the first TS2 training sequence is based on the PCIe-based protocol, the first TS2 training sequence comprises a particular symbol, and the particular symbol comprises a set of bits defined by the PCIe-based protocol to identify presence of retimers on the link, wherein the first TS2 training sequence is received in-band on the interconnect;
• regenerate the first TS2 training sequence to forward to the second device on a second link segment of the link, wherein the second link segment connects the retimer to the second device, and the first TS2 training sequence is regenerated to include a value in the set of bits to identify presence of the retimer on the link;
• send the regenerated first TS2 training sequence to the second device on the second link segment;
• and
• participate in an equalization of the link during training of the link based on the PCIe-based protocol, wherein the training of the link comprises the equalization of the link, and the equalization of the link is based on the presence of retimers on the link.

A system comprising:

• a first device;
• a second device;
• and
• a retimer, wherein the first device and the second device are coupled by a physical interconnect, the retimer is positioned between the first device and the second device on the interconnect, the retimer is to extend the physical length of a link to be established on the interconnect, and the first device comprises protocol circuitry to:
• send a particular training sequence on the interconnect in association with training of the link, wherein the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, the sent training sequence is a TS2-type training sequence based on the PCIe-based protocol, TS2-type training sequences are defined to comprise a set of symbols and a particular one of the set of symbols comprises bits defined by the PCIe-based protocol to identify whether a number of retimers are present on the link, wherein the particular training sequence is sent in-band on the interconnect;
• receive a training sequence on the interconnect during the training of the link, wherein the received training sequence is also a TS2-type training sequence, the bits in the particular symbol of the received training sequence indicate a particular number of retimers present on the link, wherein the particular number of retimers comprise the retimer;
• and
• participate with the number of retimers in equalization of the link during the training of the link, wherein training of the link comprises the equalization of the link, and the equalization of the link is based on the particular number of retimers present on the link.