System on chip having semaphore function and method for implementing semaphore function
AssigneeSamsung Electronics Co., Ltd.
InventorsDongSik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
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Abstract
A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
Claims20
A system on chip (SoC) comprising:
- a first master;
- a second master;
- an interface configured to provide communication between an external device and the first master and/or provide communication between the external device and the second master;
- and
- a controller configured to
- receive a first request to access the interface from the first master and a second request to access the interface from the second master,
- determine a first operational period for the first master in response to the first request and a second operational period for the second master in response to the second request,
- schedule the first master to have access to the interface for the first operational period and the second master to have access to the interface for the second operational period, and
- release a semaphore assigned to one of the first master and the second master when an atomic sequence of the one of the first master and the second master is completed,
- wherein the interface uses a serial data line and a serial clock line for the communication, and
- wherein the external device is shared by the first master and the second master via I2C (Inter-Integrated Circuit) interface protocol.
A system on chip (SoC) comprising:
- a plurality of masters;
- an interface configured to provide communication between an external device and the plurality of masters;
- and
- a multi-master controller configured to
- receive requests from the plurality of masters for accessing the interface,
- manage the requests by scheduling each of the plurality of masters to have access to the interface for a respective operational period, and
- release a semaphore assigned to one of the master when an atomic sequence of the one of the plurality master is completed,
- wherein the interface uses a serial data line and a serial clock line for the communication,
- wherein the external device is shared by the plurality of masters via I2C (Inter-Integrated Circuit) interface protocol, and
- wherein the multi-master controller is configured to execute an atomic sequence corresponding to each of the plurality of masters.
A device comprising:
- a first master;
- a second master;
- an interface configured to provide communication between a slave and the first master and/or provide communication between the slave and the second master;
- and
- a controller configured to
- receive a first request to access the interface from the first master and a second request to access the interface from the second master,
- determine a first operational period for the first master in response to the first request and a second operational period for the second master in response to the second request,
- schedule the first master to have access to the interface for the first operational period and the second master to have access to the interface for the second operational period, and
- release a semaphore assigned to one of the first master and the second master when an atomic sequence of the one of the first master and the second master is completed,
- wherein the interface uses a serial data line and a serial clock line for the communication, and
- wherein the interface is shared by the first master and the second master via I2C (Inter-Integrated Circuit) interface protocol.
Dependencies are inferred from the claim text.