Multi-endpoint data transport system

#This disclosure relates generally to data transport systems, and more specifically to multi-endpoint data transport systems.

#Many computing devices such as smart phones, laptop computers, and the like, have an increasing number of high-speed peripheral devices that create and/or consume data. This data is often transported to and from an application processor through a variety of cables which are often terminated with connectors. The cables and the connectors may be expensive not only with respect to cost, but also in terms of space (e.g., area and volume) needed to support the cables and connectors. Further, as the number of peripheral devices increase, so does the number of cables and connectors.

#The present embodiments are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings.

#FIG. 1 shows a block diagram of a data transport system.

#FIG. 2 shows a simplified block diagram of a context-aware time domain duplexing device, in accordance with some implementations.

#This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

#An integrated circuit is disclosed. The integrated circuit may include a first digital interface configured to transmit digital data to, and receive digital data from, a plurality of devices, a time domain duplex (TDD) physical interface (PHY) configured to transmit and receive data over a micro-coaxial cable, and a buffer coupled between the first digital interface and the TDD PHY. The buffer may be configured to aggregate the data received by the first digital interface and schedule the received data for transmission through the TDD PHY.

#A data transport system is disclosed. The data transport system may include a processor and an integrated circuit. The integrated circuit may include a first digital interface configured to transmit digital data to and receive digital data from a plurality of devices, a time domain duplex (TDD) physical interface (PHY) configured to transmit data to and receive data from the processor over a micro-coaxial cable, and a buffer coupled between the first digital interface and the TDD PHY. The buffer may be configured to aggregate the data received by the first digital interface and schedule the received data for transmission through the TDD PHY.