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US 11,599,485 B2Granted
Status check using signaling
AssigneeMicron Technology, Inc.
InventorsReshmi Basu, Jonathan S. Parry
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AssigneeMicron Technology, Inc.
InventorsReshmi Basu, Jonathan S. Parry
Estimating the term…
Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.
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Dependencies are inferred from the claim text.
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Details of memory controller: synchronisation and timing concerns
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: control signal…
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in I/O circuitry
About 14 years 5 months of term left · ends 26 Mar 2041 (estimated)
The following relates generally to one or more systems for memory and more specifically to status check using signaling.
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read, or sense, the state of one or more memory cells within the memory device. To store information, a component may write, or program, one or more memory cells within the memory device to corresponding states.
Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D Xpoint), not-or (NOR), and not-and (NAND) memory devices, and others. Memory devices may be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed states over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed states for extended periods of time even in the absence of an external power source.
FIG. 1 illustrates an example of a system that supports status check using signaling in accordance with examples as disclosed herein.
FIG. 2 illustrates an example of a system that supports status check using signaling in accordance with examples as disclosed herein.
FIG. 3 illustrates an example of a system including an encoder that supports status check using signaling in accordance with examples as disclosed herein.
Some memory systems perform a status check by status register polling. During the status register polling, the controller may poll the memory system (e.g., sending a request) to determine which memory dies are ready to receive a command. In some cases, the polling requests and responses may be communicated over one or more open NAND flash interface (ONFI) channels. Such procedures may result in an increased command overhead and decrease in channel bandwidth availability. As the quantity of memory dies increase within the memory system, the status checks may become an increasing hindrance to the efficiency of the ONFI channel.
Such techniques may result in the memory system experiencing decreased channel utilization efficiency and a performance loss when performing memory device operations, which may increase the latency for other operations related to the memory system. By performing independent status checks for memory dies, the memory system may use an increased amount of power, thereby decreasing the overall performance of the memory system. Techniques to manage status checks without compromising channel bandwidth and memory device performance are described.
Aspects of the present disclosure address the above and other deficiencies by having a memory system that reports the ready status of memory dies using signaling. The memory device may send an indication to the controller that the memory device is ready to receive commands, rather than the controller sending requests across the ONFI channels. For example, the memory system may include an output circuit that is configured to receive a ready signal from each of the memory dies. The ready signal may indicate whether a memory die is available to receive the command. In such cases, the output circuit may generate an indictor based on a value of the received ready signal and output the indicator to the controller via a pin. In some examples, the memory system may use general input/output (GPIO) pins to inform the controller of the status.