Semiconductor device having plural signal buses for multiple purposes
AssigneeMicron Technology, Inc.
InventorsKyoka Egami, Hayato Oishi, Mitsuki Koda
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Abstract
Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.
Claims20
An apparatus comprising:
- a memory cell array;
- a data junction circuit coupled to the memory cell array;
- first and second data I/O circuits each including a data I/O terminal;
- first and second signal buses;
- and
- a data interface circuit including another data I/O terminal,
- wherein the first data I/O circuit is coupled to the memory cell array via the first signal bus and the data junction circuit,
- wherein the first data I/O circuit is further coupled to the data interface circuit via the second signal bus when a first design mode is selected,
- wherein the second data I/O circuit is disconnected from the data junction circuit so as not to be able to input/output data to/from the memory cell array when the first design mode is selected, and
- wherein the second data I/O circuit is coupled to the memory cell array via the second signal bus and the data junction circuit when a second design mode is selected.
An apparatus comprising:
- a first data I/O circuit including a first data I/O terminal;
- a second data I/O circuit including a second data I/O terminal;
- a third data I/O circuit including a third data I/O terminal;
- a data interface circuit including another data I/O terminal,
- a command/address input circuit including a command/address terminal;
- a command/address interface circuit including another command/address terminal;
- a data control circuit coupled to the data I/O circuit;
- a command/address control circuit coupled to the command/address input circuit;
- a first signal bus arranged on a first wiring track, the first signal bus coupling the data control circuit to the first data I/O circuit;
- a second signal bus arranged on a first section of a second wiring track, wherein the second signal bus couples the data interface circuit to the first data I/O circuit when a first design mode is selected, and wherein the second signal bus couples the data control circuit to the second data I/O circuit when a second design mode is selected;
- and
- a third signal bus arranged on a second section of the second wiring track, wherein the third signal bus couples the command/address control circuit to the command/address interface circuit when the first design mode is selected, and wherein the third signal bus couples the data control circuit to the third data I/O circuit when the second design mode is selected.
A method for designing a semiconductor device, the method comprising:
- assigning a plurality of wiring tracks including first and second tracks;
- connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track;
- connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected;
- and
- connecting the first data I/O circuit to a second circuit by the second signal bus arranged on the second wiring track when a second design mode is selected.
Dependencies are inferred from the claim text.