Dedicated cache-related block transfer in a memory system
AssigneeRambus Inc.
InventorLiji Gopalakrishnan
Life of this patent
Estimating the term…
Abstract
A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.
Claims20
A method of a cache controller circuit in a block transfer mode, the method comprising:
- transferring first data over a first data channel between a memory controller circuit and a dynamic random access memory (DRAM) device;
- sending a block read command packet to the DRAM device via a memory controller circuit coupled between the cache controller circuit and the DRAM device;
- providing a status signal to the memory controller circuit, the status signal indicate that a second data channel between the memory controller circuit and the DRAM device is activated to perform a data transfer with a first rank of the DRAM device on behalf of a second memory device while the first data is being transferred across the first data channel between the memory controller circuit and the DRAM device;
- causing the DRAM device to enable an auxiliary data port and block read logic of the DRAM device;
- and
- receiving second data over the second data channel from the auxiliary data port;
- and
- storing the second data in a data buffer of the cache controller circuit.
A method of a cache controller circuit in a block transfer mode, the method comprising:
- transferring first data over a first data channel between a memory controller circuit and a dynamic random access memory (DRAM) device;
- sending a block write command packet to the DRAM device via a memory controller circuit coupled between the cache controller circuit and the DRAM device;
- providing a status signal to the memory controller circuit, the status signal indicate that a second data channel between the memory controller circuit and the DRAM device is activated to perform a data transfer with a first rank of the DRAM device on behalf of a second memory device while the first data is being transferred across the first data channel between the memory controller circuit and the DRAM device;
- causing the DRAM device to enable an auxiliary data port and block write logic of the DRAM device;
- storing second data in a data buffer of the cache controller circuit;
- and
- sending the second data over the second data channel to the auxiliary data port.
Dependencies are inferred from the claim text.