Systems, methods and apparatus for a storage controller with multi-mode PCIe functionalities
AssigneeSuzhou Kuhan Information Technologies Co., Ltd.
InventorsKwok Wah Yeung, Ka Wing Cheung, David Crespi
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AssigneeSuzhou Kuhan Information Technologies Co., Ltd.
InventorsKwok Wah Yeung, Ka Wing Cheung, David Crespi
Estimating the term…
A standalone Storage Controller with PCIe Multi-Mode capability that can be configured as PCIe Root-Complex (RC), an End-Point (EP) or a bridge (BR). In EP mode, the Storage Controller acts like a regular PCIe slaved controller which is connected to a PCIe Root-Complex provided by a Host via a PCIe port. While in RC mode, the Storage Controller acts as a PCIe configuration and management entity, a Host acting as a PCIe Root-Complex, which an add-in card or chip can attach to via a PCIe port that is provided by the Storage Controller, supporting any type of Network Device Interface, without an external Root-Complex. While in bridge mode, the Storage Controller can act as a transparent or non-transparent bridge with either a Root-Complex or End-Point port for the internal connection to the bridge.
A Storage Controller system comprising:
Dependencies are inferred from the claim text.
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For access to memory bus: details of memory controller
Information transfer, e.g. on bus: using universal interface adapter
Handling requests for interconnection or transfer: for access to memory bus
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus
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This application is a national phase entry under 35 U.S.C. 371 of PCT Application Serial No. PCT/CN2019/107015, filed Sep. 20, 2019, which claims priority to CN Patent Application Serial No. 201811108121.2, filed Sep. 21, 2018. The entirety of each of the foregoing is incorporated by reference.
A unique Storage Controller with Multi-Mode PCIe functionally, that can be configured as either a PCIe Root-Complex (RC), a PCIe End-Point (EP) or a bridging function (BR).
A Storage Controller, a device supporting the Peripheral Component Interface Express (PCIe) interface, traditionally provides only PCIe End-Point functionally. PCIe devices need to connect to a PCIe Root-Complex directly, or through one or more PCIe switches, in order to be configured and managed.
The drawings illustrate only exemplary embodiments of the invention and therefore do not limit its scope because the inventive concepts lend themselves to other equally effective embodiments.
FIG. 1 embodies the End-Point Mode, a more standard method of connecting a Storage Controller into an existing system. The Storage Controller can attach to the Hosts Root-Complex via a PCIe interface. The Storage Controller can then be found and configured by the Host processing complex. Multiple Storage Controllers can be attached to the compute complex at any time, but there can only be one Host base Root-Complex.
FIG. 2 embodies a Storage Controller working in a PCIe dual ported (slave) End-Point mode configuration. The Storage Controller is providing Transparent I/O Expansion to the two Hosts, each configured as a separate Root-Complex, each being attached to the Storage Controller through an external PCIe switch. The Storage Controller can have 1 to “M” PCIe Ports associated with it.
The drawings illustrate only exemplary embodiments of the invention and therefore do not limit its scope because the inventive concepts lend themselves to other equally effective embodiments. FIG. 1 shows standalone Storage Controller 101 configured in End-Point mode 100 that is comprised of one or more of the following functional elements PCIe Connector 103, PCIe PHY 104, PCIe L/T Multi-Mode RC/EP/BR 105, Logic Module 114, that may contain an embedded central processing unit (eCPU) 107, Application Logic 106, Memory Buffer 108, Storage Logic 109, Storage Interface Logic 110, Host PCIe Root Complex 102, and Storage Device 111. PCIe L/T Multi-Mode RC/EP/BR 105, configured in End-Point mode, is the PCIe controller handling the link and transport layers of the PCIe protocol. The Application logic 106 handles protocol command processing logic. The Memory Buffer 108 may consist of static random access memory (SRAM) and/or dynamic random access memory (DRAM) to buffer the data and command traffic between Application logic 106 and the storage logic 109 and storage interface logic 110. The Storage Interface Logic 110 handles the interface between the Storage Controller and Storage Device 111. The Storage Device 111 is configured and managed by the Storage Controller 101. The Storage Device 111 is connected directly to the Storage Controller 101 using the Storage Interface Logic 110. The Storage Controller could then be one or more plug-in PCIe printed circuit board (PCB) cards, or a System on a Chip (SOC) located within a storage system, also known as a target. (The Host connection could be found locally, within the target as a CPU complex with a PCIe Root-Complex, or externally, with the use of a PCIe fabric connection). An external host could be comprised of one or more of the following; a server, or any device that contains a PCIe root complex. In one embodiment, the Storage Controller 101 acts as NVMe target, the application logic 106 handles the NVMe command protocol and data processing functions, and may be assisted by the Logic Module 114 or the embedded processor subsystem complex eCPU 107.
FIG. 2 embodies a Storage Controller 200 that is located within a target and provides connectivity to a Storage Device 203. The Storage Controller 200 and the Storage Device 203 use a common interface to communicate. A Storage Controller 200 is used in this mode to allow a Host 201 direct access and control to storage in a manner that closely resembles a Host using direct attached storage (i.e. storage located within the Host). A Storage Controller 200 located in a target configured in End-Point mode, is using a PCIe Port 204 to connect to a PCIe switch 202. The PCIe switch can be internal or external to the target. The PCIe switch is connected to Hosts 201 that are configured with a PCIe fabric interface that can perform as a PCIe Root-Complex.
A PCIe Port 204 may comprise one or more of the following: a PCIe Connector 103, a PCIe PHY 104 and PCIe L/T Multi-Mode RC/EP/BR 105 logic. The port 204 is configured to operate in End-Point mode. The Storage Controller 200 may comprise two or more PCIe Port 204's. A Host 201 is a computer/server with a network interface, in this embodiment a PCIe interface, which is capable of performing as a PCIe Root-Complex. The Host may have the ability to configure and manage the Storage Controller 200 and Storage Device 203 through the Storage Controller, while the Storage Controller is acting in a Transparent Input/Output (I/O) manner.