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US 11,599,475 B2Granted
Apparatuses and methods for compute enabled cache
AssigneeMicron Technology, Inc.
InventorRichard C. Murphy
Life of this patent
Estimating the term…
Abstract
An example includes a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.
Claims20
An apparatus, comprising:
- a memory device comprising a memory array and sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations;
- a host coupled to the memory device and comprising a cache controller, the cache controller configured to:
- create a block select as metadata to a cache line to control alignment of the cache line to one or more of the plurality of compute components for processing.
An apparatus, comprising:
- a host;
- a memory device coupled to the host, functioning a last layer cache (LLC) memory, comprising a memory array and a plurality of compute components, and configured to:
- receive a cache line having block select metadata from the host processor;
- and
- operate on the block select metadata to control alignment of the cache line to one or more of the plurality of compute components for processing in the LLC memory.
2 more elements
A system for operating a cache memory, comprising:
- a host processor;
- and
- a last layer cache (LLC) memory coupled to the host processor via through silicon vias (TSVs), comprising a memory array and a plurality of compute components, and configured to:
- receive a cache line having block select metadata;
- and
- control alignment, utilizing the block select metadata, of the cache line to one or more of the plurality of compute components for processing.
3 more elements
An apparatus, comprising:
- a memory device comprising a memory array and sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations;
- a host coupled to the memory device and comprising a cache controller, the cache controller configured to:
- create a block select as metadata to a cache line to control alignment of cache blocks within the memory array;
- and
- create a subrow select as metadata to the cache line to control resource allocation of a plurality of subarrays.
2 more elements
Dependencies are inferred from the claim text.