Stacked memory dice for combined access operations

#The following relates generally to a system that includes at least one memory device and more specifically to stacked memory dice for combined access operations.

#Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices most often store one of two states, often denoted by a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read, or sense, at least one stored state in the memory device. To store information, a component of the device may write, or program, the state in the memory device.

#Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source.

#FIG. 1 illustrates an example of a system that supports stacked memory dice for combined access operations in accordance with examples as disclosed herein.

#FIG. 2 illustrates an example of a memory die that supports stacked memory dice for combined access operations in accordance with examples as disclosed herein.

#FIG. 3 illustrates an example of a system that supports stacked memory dice for combined access operations in accordance with examples as disclosed herein.

#Some memory devices may operate in environments in which a high data rate (exchanging a large amount of data in a given amount of time) between a host device and the memory device—e.g., high-bandwidth operations—is desired. Mobile systems, among others, may be one example of such environments. In some examples, increasing pin count of the system (e.g., increased pin count of the memory device) may facilitate increased bandwidth (e.g., an increased maximum data rate) but may increase cost and complexity of the system—e.g., due to increased package size (e.g., for package on package (PoP) implementations), increased complexity of an associated printed circuit board (PCB) layout—or may have other drawbacks. In some cases, increasing a clock speed of the memory device may facilitate increased bandwidth (e.g., an increased maximum data rate) but an extent to which the clock speed may be increased may be limited in practice by power, efficiency, circuit complexity, timing margin, or other constraints.

#Apparatuses including stacked memory dice and operations of the same are described which may, for example, support increased bandwidth between a memory device and other devices, such as a host device for the memory device. Further, the devices and techniques described herein may not be dependent upon increased pin count or clock rates or may have other benefits. For example, the apparatus may include multiple memory dice (e.g., stacked memory dice above a substrate). One memory die may be configured as a master die, and one or more other memory dice may each be configured as a slave die. The master die may be coupled with and communicate with a host device. A slave die may be coupled with the master die but otherwise not connected with the host device. In response to a read command, the memory device may execute a prefetch operation in which the master die provides a first subset of prefetched data (e.g., a first half of the prefetched data) and the slave die provides a second subset of prefetched data (e.g., a second half of the prefetched data). For example, the master die and the slave die may each be configured to support prefetching a certain amount of data, which may be referred to as a prefetch size, and the total amount of prefetched data (data prefetched by the memory device in response to the read command) may be double the prefetch size.

#In some cases, the master die may output the second subset of data immediately following the first subset of data (e.g., no time delay or time bubble) to provide the set of data associated with the read command to the host device. Further, the master die may support both binary signaling and multi-level signaling for exchanging data with the host device. For example, the master die may receive, from the host device, an indication of whether to use binary signaling or multi-level signaling to output the set of data associated with the read command (e.g., an indication of a data rate to support certain bandwidths). In some cases, the master die may select, based on the indicated or an otherwise determined data rate, a modulation scheme from a set that includes a higher-order (non-binary) modulation scheme (e.g., pulse amplitude modulation 3 (PAM3) or pulse amplitude modulation 4 (PAM4) signaling) and a binary modulation scheme (e.g., pulse amplitude modulation 2 (PAM2) signaling or non-return-to-zero (NRZ) signaling) and output the set of data using the selected modulation scheme. For example, the use of PAM4 signaling to output the data to the host device in conjunction with the prefetch of data from both the master die and the slave die may support a prefetch operation that provides, in response to the read command, an increased amount of data (e.g., doubled relative to the per-die prefetch size) in the same amount of time without needing an increase in data bus width (pin count), an increase in clock rate, or an adjustment in the per-die prefetch size (which may, for example, avoid a redesign of various related aspects of each memory die).