Interleaved cache prefetching
AssigneeMicron Technology, Inc.
InventorsLaurent Isenegger, Robert M. Walker, Cagdas Dirik
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsLaurent Isenegger, Robert M. Walker, Cagdas Dirik
Estimating the term…
A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.
A method, comprising:
A system, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with prefetch
Specifically adapted to achieve a particular effect: improving I/O performance
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: controller…
In-line storage system: plurality of storage devices
About 14 years 10 months of term left · ends 1 Sep 2041 (estimated)
Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to memory sub-system prefetching into interleaved caches.
A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.
The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.
FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure.
FIG. 2 is an example system that includes a memory device having a controller for interleaved cache prefetching in accordance with some embodiments of the present disclosure.
Aspects of the present disclosure are directed to memory sub-system prefetching into interleaved caches, in particular to memory sub-systems that include a prefetching component. A memory sub-system can be a storage system, storage device, a memory module, or a combination of such. An example of a memory sub-system is a storage system such as a solid-state drive (SSD). Examples of storage devices and memory modules are described below in conjunction with FIG. 1, et alibi. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.
Server systems can use a plurality of memory channels interleaved. The interleaving granularity dictates which channel is servicing memory requests issued by a host memory controller. For example, a 64B interleaving granularity means that the bytes addressed from 0 to 63 are serviced by channel 0, 64 to 127 by channel 1, and so on until the last channel number is reached. After the last channel, a return to channel 0 is made. A 128B interleaving granularity would instead allocate addresses 0 to 127 to channel 0, 128 to 255 to channel 1, etc.
Some memory technologies and interfaces allow the deployment of hybrid memory subsystems. These hybrid memory subsystems may include a cache for quick access to “hot” data and a backing store with slower data access times for “cold” data. Prefetching is a technique that allows for proactively bringing data from a backing store into a cache in anticipation of future accesses that might be requested by the host memory controller. Prefetching can improve system performance and reduce latencies.