Cache for storing coherent and non-coherent data

#The present disclosure relates to a data processing system. More particularly, the present disclosure relates to a cache for a data processing system.

#A data processing system may include a system-on-chip (SoC) with various components that are connected by one or more interconnects. Generally, certain components process data, such as, for example, processors, such as central processing units (CPUs) and CPU clusters, accelerators such as graphics processing units (GPUs) and GPU clusters, etc., while other components send data to, and receive data from, the data processing components, such as, for example, memory controllers, input/output (I/O) controllers, network interface controllers, etc. These data provisioning components may be connected to on-chip or off-chip memory, data buses, wired or wireless networks, etc. The interconnect provides the network infrastructure over which data transactions between components are conveyed. The data processing system may be divided into coherent domains and non-coherent domains.

#A cache that stores coherent data resides within a coherent domain of the data processing system, and is coupled to (or resides within) a coherent interconnect. The coherent interconnect generates appropriate snoops and management transactions to maintain data coherency without additional software management by the various components or agents. Any agent that uses this cache must also reside within the coherent domain. A coherent cache does not store data from a non-coherent domain.

#FIG. 1A depicts a block diagram for a system with a coherent domain, in accordance with an embodiment of the present disclosure.

#FIG. 1B depicts a block diagram for the system depicted in FIG. 1A using protocol node nomenclature, in accordance with an embodiment of the present disclosure.

#FIG. 2 depicts a block diagram for a system with coherent and non-coherent domains, in accordance with an embodiment of the present disclosure.

#Embodiments of the present disclosure will now be described with reference to the drawing figures, in which like reference numerals refer to like parts throughout.

#Embodiments of the present disclosure advantageously provide a single cache that stores both coherent data and non-coherent data by tracking which cache lines store shareable data from the coherent domain and which cache lines store non-shareable data from the non-coherent domain. Cache lines are dynamically allocated as either shareable (i.e., coherent) or non-shareable (i.e., non-coherent), which advantageously enlarges the caching resource available to the coherent and non-coherent domains.

#In addition to identifying and storing shareable and non-shareable data from the coherent and non-coherent domains, respectively, the cache advantageously functions as an eviction cache for the coherent domain by caching shareable clean evictions, and enables the migration of dirty shareable cache lines back into the coherent domain without writing the cache line data to memory. The cache is located closer to off-chip memory, to reduce average latencies compared with memory and reduce off-chip memory traffic, and away from the coherent domain, where area and latency are at a premium. Additionally, when the cache usage is modal with bursts of activity in each domain, the cache may be maximally occupied.