Stacked memory device and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJoonsik Sohn, Hyunjoong Kim, Woongjae Song, Soowoong Ahn, Seunghyun Cho, Jihyun Choi
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Abstract
According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.
Claims20
A method of operating a stacked memory device including a plurality of memory chips stacked in a vertical direction, the method comprising:
- receiving a command and an address from a memory controller;
- determining chip IDs each indicating one memory chip among the plurality of memory chips by decoding the address;
- and
- sequentially accessing at least two memory chips among the plurality of memory chips based on the chip IDs such that the at least two memory chips are non-adjacent,
- wherein a memory chip corresponding to an (N+1)th chip ID among the plurality of memory chips is arranged below memory chips corresponding to an Nth chip ID and an (N+2)th chip ID, respectively.
A stacked memory device comprising a plurality of memory dies stacked in a vertical direction,
- wherein the plurality of memory dies comprise:
- a first memory die;
- a third memory die electrically connected to the first memory die through first TSVs;
- and
- a second memory die between the first memory die and the third memory die,
- wherein the second memory die is not connected to the first TSV, and
- wherein two memory dies adjacent to each other among the plurality of memory dies are not accessed at the same time.
A memory system comprising:
- a memory device on an interposer and including a plurality of memory dies stacked in a vertical direction;
- and
- a memory controller adjacent to the memory device on the interposer, configured to generate a stack ID indicating a subset of the plurality of memory dies, and transmit the generated stack ID to the memory device,
- wherein the memory device includes control logic circuitry configured to cause the memory device to access at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.
Dependencies are inferred from the claim text.