System recovery using a failover processor

#Each of following applications are hereby incorporated by reference: application Ser. No. 16/579,294 filed on Sep. 23, 2019; application Ser. No. 15/665,343 filed on Jul. 31, 2017. The Applicant hereby rescinds any disclaimer of claim scope in the parent application(s) or the prosecution history thereof and advises the USPTO that the claims in this application may be broader than any claim in the parent application(s).

#The present disclosure relates to system recovery. In particular, the present disclosure relates to system recovery in a system with more than one processor.

#Computer systems are used to perform many different types of operations. A computer system relies on at least one processor, as described in further detail below. Each processor has an associated instruction set, i.e., a set of instructions that the processor is able to understand and execute natively. A given instruction set may include instructions for data handling, memory operations, arithmetic and logic operations, and control flow operations (e.g., branching, conditional logic, and calling other code). An instruction set may also include instructions for communicating with a coprocessor. A coprocessor is another processor, which may have a different instruction set, that supplies functionality in addition to the functionality of a primary processor. If a processor in a computer system fails, the entire computer system may be rendered inoperable. If the computer system has multiple processors and/or coprocessors, functionality supplied by the failed processor may no longer be available. Thus, even if the computer system as a whole remains operable, the failure of the processor may effectively render the computer system inoperable for its intended purpose.

#The embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and they mean at least one. In the drawings:

#FIG. 1A is a block diagram illustrating a system in accordance with one embodiment;

#FIGS. 1B and 1C are block diagrams illustrating a module in accordance with one embodiment;

#In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding. One or more embodiments may be practiced without these specific details. Features described in one embodiment may be combined with features described in a different embodiment. In some examples, well-known structures and devices are described with reference to a block diagram form in order to avoid unnecessarily obscuring the present invention. 1. GENERAL OVERVIEW 2. ARCHITECTURAL OVERVIEW AND EXAMPLES 3. SYSTEM RECOVERY USING A FAILOVER PROCESSOR 4. ILLUSTRATIVE EXAMPLE 5. MISCELLANEOUS; EXTENSIONS 6. HARDWARE OVERVIEW 7. COMPUTER NETWORKS AND CLOUD NETWORKS

#In one embodiment, a first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. The second processor fails to execute at least one operation of the second type within a particular period of time. Responsive to determining that the failure has occurred, the first processor is configured to execute both the operations of the first type and the operations of the second type.

#One or more embodiments described in this Specification and/or recited in the claims may not be included in this General Overview section.