Electronic system including error calculation circuit for performing error correction operation
AssigneeSK hynix Inc.
InventorIn Sung Koh
Life of this patent
Estimating the term…
Abstract
An electronic system includes a controller configured to output a clock, a command, and an address, and configured to receive and transmit data. The electronic system also includes a semiconductor device including an error calculation circuit. The semiconductor device is configured to generate, by the error calculation circuit, a parity including information on an error included in transfer data generated from the data, in a write operation initiated by the command, and to generate, by the error calculation circuit, a syndrome including information on an error included in transfer data generated from internal data, in a read operation initiated by the command.
Claims21
An electronic system comprising:
- a controller configured to output a clock, a command, and an address, and configured to receive and transmit data;
- and
- a semiconductor device including an error calculation circuit,
- wherein the semiconductor device is configured to generate, by the error calculation circuit:
- a parity including information on an error included in first transfer data generated from the data, in a write operation initiated by the command;
- and
- a syndrome including information on an error included in second transfer data generated from internal data, in a read operation initiated by the command, wherein, the first transfer data and the second transfer data are loaded on same input/output line, and
- wherein the semiconductor device comprises:
- a control circuit configured to generate a mode setting signal, a write signal, and a read signal depending on a logic level combination of the command;
- a data input/output circuit configured to output the first transfer data, generated by receiving the data, loaded on an input/output line in the write operation, and configured to output the second transfer data, loaded on the input/output line, as the data in the read operation;
- and
- the error calculation circuit configured to generate an error correction enable signal when the mode setting signal is enabled and any one of the write signal and the read signal is enabled, and configured to generate the parity and the syndrome including error information depending on a result of calculating bits included in the first transfer data and the second transfer data loaded on the input/output line.
An electronic system comprising:
- a control circuit configured to generate a mode setting signal, a write signal, and a read signal depending on a logic level combination of a command;
- and
- an error calculation circuit configured to:
- generate an error correction enable signal and generate a parity including error information depending on a result of calculating bits included in first transfer data loaded on an input/output line, in a write operation in which the mode setting signal is enabled and the write signal is inputted;
- and
- generate the error correction enable signal and generate a syndrome including error information depending on a result of calculating bits included in second transfer data loaded on the input/output line, in a read operation in which the mode setting signal is enabled and the read signal is inputted.
Dependencies are inferred from the claim text.