Integrity check device for safety sensitive data and electronic device including the same

An electronic device comprising:

• a host device;
• and
• a first integrity check device controlled by the host device, the first integrity check device configured to store a plurality of first safety sensitive data forming a first codeword that is a single codeword, to perform an operation of checking an error in the plurality of first safety sensitive data based on a cyclic redundancy check (CRC) calculation, and to perform an operation of updating a first reference CRC parity value, and
• wherein the first integrity check device includes:
• a first register array including a plurality of first registers that store the plurality of first safety sensitive data;
• and
• first processing circuitry configured to
• generate a first current CRC parity value by sequentially performing the CRC calculation on the plurality of first safety sensitive data, to store the first reference CRC parity value,
• output a first check result signal indicating whether the error occurs by activating a first path and by comparing the first current CRC parity value with the first reference CRC parity value when the plurality of first safety sensitive data are maintained and when the operation of updating the first reference CRC parity value is unnecessary, and
• update the first reference CRC parity value to the first current CRC parity value by activating a second path when at least one of the plurality of first safety sensitive data is intentionally changed and when the operation of updating the first reference CRC parity value is necessary,
• wherein the first processing circuitry is further configured to
• deactivate the second path in response to the first path being activated, and
• deactivate the first path in response to the second path being activated, and
• wherein the first path includes first hardware and the second path includes second hardware different from the first hardware.

An integrity check device comprising:

• a register array including a plurality of registers that store a plurality of safety sensitive data forming one codeword and receive a plurality of write enable signals;
• processing circuitry configured to
• sequentially output the plurality of safety sensitive data stored in the plurality of registers based on a register selection signal;
• generate a current CRC parity value by sequentially performing a CRC calculation on the plurality of safety sensitive data provided;
• based on a CRC calculation done signal, output the current CRC parity value;
• output the current CRC parity value to a first path or a second path based on a parity update signal;
• store a reference CRC parity value;
• generate a check result signal indicating whether an error occurs by comparing the current CRC parity value with the reference CRC parity value;
• based on the parity update signal, provide the check result signal as a final output signal through the first path or provide a masking signal for masking an occurrence of the error as the final output signal through the second path;
• and
• generate the register selection signal, the CRC calculation done signal and the parity update signal,
• wherein, when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, the first path is activated to provide the check result signal as the final output signal,
• wherein, when at least one of the plurality of write enable signals is activated, when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary, the second path is activated to update the reference CRC parity value to the current CRC parity value and to provide the masking signal as the final output signal, and
• wherein, when it is determined that the at least one of the plurality of safety sensitive data is intentionally reset or modified while the CRC calculation is sequentially performed on the plurality of safety sensitive data, the reference CRC parity value is updated during a current CRC calculation round or a next CRC calculation round based on whether the CRC calculation is performed on safety sensitive data that is reset or modified,
• wherein the processing circuitry is further configured to
• deactivate the second path in response to the first path being activated, and
• deactivate the first path in response to the second path being activated, and
• wherein the first path includes first hardware and the second path includes second hardware different from the first hardware.