Dual mode hardware reset

#Memory devices are semiconductor circuits that provide electronic storage of data for a host system (e.g., a computer or other electronic device). Memory devices may be volatile or non-volatile. Volatile memory requires power to maintain data, and includes devices such as random-access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistive random-access memory (RRAM), or magnetoresistive random access memory (MRAM), among others.

#Host systems (e.g., hosts) typically include a host processor, a first amount of host memory (e.g., main memory, often volatile memory, such as DRAM) to support the host processor, and one or more storage systems (e.g., often non-volatile memory, such as flash memory) that provide additional storage to retain data in addition to or separate from the main memory.

#A storage system (e.g., a solid-state drive (SSD), a universal flash storage (UFS) device, etc.) can include a memory controller and one or more memory devices, including a number of (e.g., multiple) dies or logical units (LUNs). In certain examples, each die can include a number of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller can include interface circuitry configured to communicate with a host device (e.g., the host processor or interface circuitry) through a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller can receive commands or operations from the host system in association with memory operations or instructions, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory devices and the host device, erase operations to erase data from the memory devices, perform drive management operations (e.g., data migration, garbage collection, block retirement), etc.

#In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

#FIG. 1 illustrates an example host system including a host device and a storage system.

#FIG. 2 illustrates example table illustrating different parameters and resulting wake latency and power savings for different storage system configurations.

#Modern host systems, including a host device, a storage system, and a communication interface, have different power modes, including, for example, a normal (e.g., active) mode, one or more levels of power-saving modes, such as a sleep mode, and an off mode. In various sleep modes, certain system resources are powered down to save power, but the communication interface can remain active or in a reduced power state (above power down). Further, many host systems share power rails throughout the system, preventing power removal from the storage system alone, thus limiting power savings. Accordingly, host systems may additionally include other power modes, such as a deep sleep mode configured to allow the host system to power down most or all of the communication interface between the storage system and a host device to further reduce power consumption of the host system, such as in contrast to the sleep mode.

#For example, in UFS systems, the deep sleep mode can cease communication between the host device and the storage system on the upstream and downstream lanes of the communication interface (e.g., DIN_t, DIN_c and DOUT_t, DOUT_c, respectively), but maintain a unidirectional hardware (HW) reset signal interface from the host device to the storage system separate from the upstream and downstream lanes.

#When in the deep sleep mode, a power cycle or hardware reset signal may be required to return the storage system or the communication interface to the normal mode. The host device traditionally controls the deep sleep mode. Because the host cannot monitor the storage system while the communication interface is powered down, at a return to normal mode, the host device can re-initialize the storage system to place it in a known state to continue normal operation. Such traditional re-initialization takes a certain amount of time.