Coalescing adjacent gather/scatter operations

A method comprising:

• caching data in a data cache;
• caching instructions in an instruction cache;
• decoding the instructions, including a first instruction, the first instruction having a first field specifying a first destination vector register, the first instruction having a second field specifying a 64-bit general-purpose register as a source of a base address, the first instruction having a third field specifying a mask register as a source of a mask, and the first instruction indicating a data element width of 64-bits;
• and
• executing the first instruction, including:
• for mask bits of the mask that are one:
• loading a corresponding structure from a memory based on the base address, the structure including, as contiguous elements in the memory, a first 64-bit data element, a second 64-bit data element, and a third 64-bit data element;
• and
• storing the first 64-bit data element in a 64-bit data element position of the first destination vector register corresponding to the mask bit, the second 64-bit data element in a 64-bit data element position of a second destination vector register corresponding to the mask bit, and the third 64-bit data element in a 64-bit data element position of a third destination vector register corresponding to the mask bit;
• and
• for mask bits of the mask that are zero, not loading the corresponding structure from the memory.

A system comprising:

• a system memory;
• and
• a processor coupled with the system memory, the processor comprising:
• a data cache to cache data;
• an instruction cache to cache instructions;
• a decode unit coupled to the instruction cache, the decode unit to decode the instructions, including a first instruction, the first instruction having a first field to specify a first destination vector register, the first instruction having a second field to specify a 64-bit general-purpose register as a source of a base address, the first instruction having a third field to specify a mask register as a source of a mask, and the first instruction to indicate a data element width of 64-bits;
• and
• an execution unit coupled to the decode unit, coupled to the first destination vector register, and coupled to the 64-bit general-purpose register, the execution unit based on the first instruction to:
• for mask bits of the mask that are one:
• load a corresponding structure from a memory based on the base address, the structure to include, as contiguous elements in the memory, a first 64-bit data element, a second 64-bit data element, and a third 64-bit data element;
• and
• store the first 64-bit data element in a 64-bit data element position of the first destination vector register corresponding to the mask bit, the second 64-bit data element in a 64-bit data element position of a second destination vector register corresponding to the mask bit, and the third 64-bit data element in a 64-bit data element position of a third destination vector register corresponding to the mask bit;
• and
• for mask bits of the mask that are zero, not load the corresponding structure from the memory.

A system on a chip (SoC) comprising:

• a memory controller unit;
• and
• a processor core coupled with the memory controller unit, the processor core comprising:
• a data cache to cache data;
• an instruction cache to cache instructions;
• a decode unit coupled to the instruction cache, the decode unit to decode the instructions, including a first instruction, the first instruction having a first field to specify a first destination vector register, the first instruction having a second field to specify a 64-bit general-purpose register as a source of a base address, the first instruction having a third field to specify a mask register as a source of a mask, and the first instruction to indicate a data element width of 64-bits;
• and
• an execution unit coupled to the decode unit, coupled to the first destination vector register, and coupled to the 64-bit general-purpose register, the execution unit based on the first instruction to:
• for mask bits of the mask that are one:
• load a corresponding structure from a memory based on the base address, the structure to include, as contiguous elements in the memory, a first 64-bit data element, a second 64-bit data element, and a third 64-bit data element;
• and
• store the first 64-bit data element in a 64-bit data element position of the first destination vector register corresponding to the mask bit, the second 64-bit data element in a 64-bit data element position of a second destination vector register corresponding to the mask bit, and the third 64-bit data element in a 64-bit data element position of a third destination vector register corresponding to the mask bit;
• and
• for mask bits of the mask that are zero, not load the corresponding structure from the memory.

A machine-readable medium storing instructions that when executed are to cause a machine to perform operations, including to:

• decode a first instruction, the first instruction having a first field to specify a first destination vector register, the first instruction having a second field to specify a 64-bit general-purpose register as a source of a base address, the first instruction having a third field to specify a mask register as a source of a mask, and the first instruction to indicate a data element width of 64-bits;
• and
• execute the first instruction, including to:
• for mask bits of the mask that are one:
• load a corresponding structure from a memory based on the base address, the structure to include, as contiguous elements in the memory, a first 64-bit data element, a second 64-bit data element, and a third 64-bit data element;
• and
• store the first 64-bit data element in a 64-bit data element position of the first destination vector register corresponding to the mask bit, the second 64-bit data element in a 64-bit data element position of a second destination vector register corresponding to the mask bit, and the third 64-bit data element in a 64-bit data element position of a third destination vector register corresponding to the mask bit;
• and
• for mask bits of the mask that are zero, not load the corresponding structure from the memory.