AI synaptic coprocessor

#This application is based upon provisional application Ser. No. 63/124,923, filed Dec. 14, 2020, the disclosure which is hereby incorporated by reference in its entirety.

#The present invention relates to the field of computers, and more particularly, this invention relates to coprocessors used with computers, such as for artificial intelligence applications.

#Artificial intelligence applied to many computer applications has grown in recent years and placed demands on the computational power of normal processors. For example, processor speeds have almost reached a maximum at about 4 GHz, ending the gains that have been reached through increased clock speeds as transistor dimensions shrink based upon Moore's law. As semiconductor technology advances and gate lengths decrease, greater numbers of gates are placed on one chip, often more than 10 billion gates per chip. It is becoming increasingly difficult to place even greater numbers of gates on chips. One approach is to place more processors on each chip, but this requires partitioning the processing workload, synchronizing the tasks, and feeding the input and output to all processors.

#Other objects, features and advantages of the present invention will become apparent from the Detailed Description of the invention which follows, when considered in light of the accompanying drawings in which:

#FIG. 1 is a block diagram of the synaptic coprocessor showing basic components in accordance with a non-limiting example.

#FIG. 2 is a block diagram of the synaptic coprocessor of FIG. 1 showing a single processing pipeline as an example data transport among components.

#Different embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments are shown. Many different forms can be set forth and described embodiments should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope to those skilled in the art.

#Referring now to FIG. 1, there is illustrated at 100 the synaptic coprocessor that includes a processor 104 that communicates with external devices outside the synaptic coprocessor via a serial input and output port 108, and may receive and send interrupts and real-time clock signals. The synaptic coprocessor 100 includes 64-bit address and data buses 112 that communicate with other devices outside the synaptic coprocessor. A local 64-bit memory 116 is included within the synaptic coprocessor 100 that stores conventional length data. DMA logic 120 that may include DMA controller functionality may be connected to the processor 104 and to a very long data word (VLDW) memory 124 in this example. In another aspect described below with reference to FIG. 11B, a buffer may be used. The DMA controller 120 is configured to address and control the transfer of test very long data words (VLDWs) from the very long data word memory 124 to the processing logic unit 128, which includes a plurality of processing pipelines 130 as illustrated by Pipeline No. 1 to Pipeline No. N. The very long data word memory 124 is configured to store a plurality of very long data words, each formed as a test very long data word (VLDW) having a length in the range of about 1,000 bits to 1 million or more bits and containing encoded information that is distributed across the length of the VLDW. The number and range of bits may vary. The VLDW memory 124 may include RAM. The very long data words are also referred to as Elastic Representation VLDWs and designed for knowledge representation in applications such as artificial intelligence and next generation databases as explained in greater detail below. The illustrated processor 104, processing logic unit 128, and memory 124 may contain registers for holding data, such as conventional length, e.g., 64-bit words, or very long data words as described above.

#The processor 104 is configured to generate search terms and the processing logic unit 128 is configured to receive a test VLDW from the VLDW memory 124 and receive a search term that had been generated from the processor and compute a Boolean inner product between the search term and the test VLDW read from memory 124 indicative of the measure of similarity between the test VLDW and at least one search term (FIG. 2). The very long data word may include encoded information that is distributed across the length of the very long data word as a pseudorandom number, and in an example, include a globally random and locally ordered linear array of data. The search term may be a VLDW, and in an example, by processing in an attention processing unit 134 (FIG. 3), and which is part of the processing logic unit 128, may be converted into a focused search term that is modified from an original search term as a VLDW to express or extinguish features of interest as explained below. In an example, the processing logic unit 128 may be configured to operate on successive test VLDWs compared against a search term. In an example, the attention processing unit 134 is operative with a vector processing unit 138, which includes a scoring logic unit 142.