Pre-staged instruction registers for variable length instruction set machine
AssigneeTenstorrent Inc.
InventorsMiles Robert Dooley, Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac
Life of this patent
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Abstract
Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.
Claims21
A processor comprising:
- an instruction memory;
- at least one functional processing unit;
- a bus;
- a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory;
- and
- a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.
A method, in which each step is conducted by a processor, comprising:
- storing instructions in an instruction memory;
- loading a set of pre-staged instructions from the instruction memory to a set of instruction registers using a bus;
- receiving an instruction at a logic circuit;
- and
- providing, in response to receiving the instruction and using the logic circuit, the pre-staged instructions from the set of instruction registers to at least one functional processing unit.
A processor comprising:
- an instruction memory;
- at least one functional processing unit;
- a bus;
- a set of instruction registers;
- a means for loading the set of instruction registers with a set of pre-staged instructions using the bus;
- and
- a means for providing the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.
Dependencies are inferred from the claim text.