Memory device
AssigneeSK hynix Inc.
InventorYo Sep Lee
Life of this patent
Estimating the term…
Abstract
A memory device includes a data storage circuit configured to access a cell array having first data stored therein when an arithmetic active operation is performed, output the first data when a first read operation is performed, access a cell array having second data stored therein when an active operation is performed, and output the second data when a second read operation is performed. The memory device also includes an arithmetic circuit configured to receive latch data generated through the first read operation and read data generated through the second read operation, and perform an arithmetic operation on the latch data and the read data.
Claims21
A memory device comprising:
- a data storage circuit configured to:
- access a first cell array having first data stored therein when an arithmetic active operation is performed,
- output the first data when a first read operation is performed,
- access a second cell array having second data stored therein when an active operation is performed, and
- output the second data when a second read operation is performed;
- and an arithmetic circuit configured to:
- receive latch data generated through the first read operation and read data generated through the second read operation, and
- perform an arithmetic operation on the latch data and the read data.
A memory device comprising:
- a row control circuit configured to:
- receive an arithmetic row address which is generated when an arithmetic active operation is performed, and
- control a data storage circuit to access a first cell array having first data stored in the first cell array;
- a column control circuit configured to:
- receive a first column address which is generated when a first read operation is performed, and
- control the data storage circuit to output the first data stored in the first cell array accessed by the arithmetic active operation;
- and
- a data latch circuit configured to:
- latch the first data based on a latch control signal, and
- output the latched first data as latch data used for an arithmetic operation.
A memory device comprising:
- a row control circuit configured to:
- receive an arithmetic row address which is generated when an arithmetic active operation is performed,
- control a data storage circuit to access a first cell array having first data stored in the first cell array,
- receive a row address which is generated when an active operation is performed, and
- control the data storage circuit to access a second cell array having second data stored in the second cell array;
- a column control circuit configured to:
- receive a first column address which is generated when a first read operation is performed,
- control the data storage circuit to output the first data stored in the first cell array accessed by the arithmetic active operation,
- receive a second column address which is generated when a second read operation is performed, and
- control the data storage circuit to output the second data stored in the second cell array accessed by the active operation;
- a data latch circuit configured to:
- latch the first data based on a latch control signal, and
- output the latched first data as latch data;
- an input/output sense amplifier configured to generate read data by sensing and amplifying the second data when the second read operation is performed;
- and
- an arithmetic circuit configured to perform an arithmetic operation on the latch data and the read data.
Dependencies are inferred from the claim text.