Semiconductor memory device and system including the same

A system, comprising:

• a semiconductor memory device;
• and
• a host device including a memory controller configured to control the semiconductor memory device, wherein:
• the semiconductor memory device includes:
• an interface semiconductor die including a plurality of command pins configured to receive a plurality of command signals, which are transferred from the memory controller, and including an interface command decoder configured to decode the plurality of command signals;
• a memory semiconductor die stacked with the interface semiconductor die, the memory semiconductor device including a memory integrated circuit configured to store data, and including a memory command decoder configured to decode the plurality of command signals, which are transferred from the interface semiconductor die;
• and
• a plurality of through-silicon vias electrically connecting the interface semiconductor die and the memory semiconductor die,
• the interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller,
• the interface command decoder is configured to generate an interface clock enable signal to control a first clock supply with respect to the interface semiconductor die based on a power mode command, which is transferred through the plurality of command pins from the memory controller, and
• the memory command decoder is configured to generate a memory clock enable signal to control a second clock supply with respect to the memory semiconductor die based on the power mode command, which is transferred through the plurality of through-silicon vias from the interface semiconductor die.

A semiconductor memory device, comprising:

• an interface semiconductor die including a plurality of command pins configured to receive a plurality of command signals, which are transferred from a memory controller, and including an interface command decoder configured to decode the plurality of command signals;
• a memory semiconductor die including a memory integrated circuit configured to store data, and including a memory command decoder configured to decode the plurality of command signals, which are transferred from the interface semiconductor die;
• and
• a plurality of internal command paths electrically connecting the interface semiconductor die and the memory semiconductor die, wherein:
• the interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller,
• the interface command decoder is configured to generate an interface clock enable signal to control a first clock supply with respect to the interface semiconductor die based on a power mode command, which is transferred through the plurality of command pins from the memory controller, and
• the memory command decoder is configured to generate a memory clock enable signal to control a second clock supply with respect to the memory semiconductor die based on the power mode command, which is transferred through the plurality of internal command paths from the interface semiconductor die.