Timing generator, timing generating method, and associated control chip

#The present invention is related to the generation of timing signals, and more particularly, to a timing generator, a timing generating method and a control chip, which can generate arbitrary digital signal waveforms.

#There are many methods for generating digital signal waveforms: for example, by controlling general-purpose input/output (GPIO) or by utilizing a universal asynchronous receiver/transmitter (UART). These methods have certain disadvantages, however. For example, the UART is limited to the precision of the related hardware, and is therefore unable to reach nanosecond level precision. In addition, if high precision is required, states need to be continuously switched through a certain type of loop (e.g. a specific command such as while loop) under a condition of disabling interruption, which may greatly occupy computational resources of a central processing unit (CPU). In another example, utilizing the UART also introduces the problem of occupying the computational resources of the CPU. In addition, due to characteristics of the UART, the UART cannot generate arbitrary digital signal waveforms.

#Thus, there is a need for a novel timing generator and timing generating method which can solve the problems of the related art without introducing any side effect or in a way that is less likely to introduce side effects.

#FIG. 1 is a diagram illustrating a control chip according to an embodiment of the present invention.

#FIG. 2 is a diagram illustrating a timing data set according to an embodiment of the present invention.

#FIG. 3 illustrates some implementation details of the control chip shown in FIG. 1 according to an embodiment of the present invention.

#FIG. 1 is a diagram illustrating a control chip 10 according to an embodiment of the present invention. The control chip 10 may comprise a storage device 20, a timing generator 100 coupled to the storage device 20, and a processing circuit 50 coupled to the timing generator 100, where the storage device 20 may be implemented by a Synchronous Dynamic Random Access Memory (SDRAM) utilizing a Double Data Rate (DDR) technology, and the processing circuit 50 may be implemented by a central processing unit (CPU), but the present invention is not limited thereto. In this embodiment, the timing generator 100 may comprise a receiving circuit 120, a transmitting circuit 140 coupled to the receiving circuit 120, and a control unit 160 respectively coupled to the receiving circuit 120 and the transmitting circuit 140. In addition, the timing generator 100 may further comprise a buffer 180 coupled between the receiving circuit 120 and the transmitting circuit 140 (e.g. the transmitting circuit 140 is coupled to the receiving circuit 120 through the buffer 180) to buffer data transmitted from the receiving circuit 120 to the transmitting circuit 140, where the buffer 180 may comprise a first input first output (FIFO) memory, but the present invention is not limited thereto.

#In operations of the control chip 10, the storage device 20 may be configured to store one or more timing data sets (e.g. a series of timing data sets), and the processing circuit 50 may be configured to transmit at least one command to the control unit 160 to control operations of the timing generator 100. In the operations of the timing generator 100, the receiving circuit 120 may be configured to receive the one or more timing data sets (e.g. the series of timing data sets) from the storage device 20; for example, the buffer 180 may receive the series of timing data sets from the receiving circuit 120, and sequentially transmit each timing data set within the series of timing data sets to the transmitting circuit 140. The transmitting circuit 140 may be configured to select a specific signal type within multiple signal types according to a timing data set (e.g. each timing data set within the series of timing data sets) within the one or more timing data sets (e.g. the series of timing data sets), and output an output signal VOUT having the specific signal type with a specific time length, wherein the timing data set indicates the specific signal type and the specific time length. The control unit 160 may be configured to control operations of the receiving circuit 120 and the transmitting circuit 140.

#In this embodiment, the multiple signal types may at least comprise one or more of pulse width modulation (PWM), a first fixed level, and a second fixed level different from the first fixed level. In addition, the control unit 160 may control settings such as a frequency and a duty cycle of the PWM according to commands transmitted by the processing circuit 50, where the frequency and the duty cycle of the PWM may carry information or may be determined according to some design requirements.