Dynamic adjustment of root clock frequency in logic system design during verification

An apparatus for dynamically adjusting a root clock frequency of a logic system design, comprising:

• a memory storing program instructions;
• and
• a processor configured to execute the program instructions to:
• identify a plurality of signal paths from one of a plurality of signal inputs of the logic system design to one of a plurality of signal outputs of the logic system design, each of the plurality of signal paths having a signal propagation delay;
• determine a state of an input signal to a target signal input in a current root clock cycle using a check logic placed at the target signal input;
• determine a target signal path from the plurality of signal paths in the current root clock cycle based on the state of the input signal to the target signal input in the current root clock cycle and one or more logic devices along each signal path associated with the target signal input;
• and
• determine the root clock frequency for the logic system design based on a longest signal propagation delay of the signal propagation delays of the plurality of signal paths excluding the target signal path;
• controlling, according to the determined root clock frequency, an emulation process of the logic system design on the emulation system.

A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of an electronic system to cause the electronic system to perform a method for dynamically adjusting a root clock frequency of a logic system design on an emulation system, the method comprising:

• identifying a plurality of signal paths from one of a plurality of signal inputs of the logic system design to one of a plurality of signal outputs of the logic system design, each of the plurality of signal paths having a signal propagation delay;
• determining a state of an input signal to a target signal input in a current root clock cycle using a check logic placed at the target signal input;
• determining a target signal path from the plurality of signal paths in the current root clock cycle based on the state of the input signal to the target signal input in the current root clock cycle and one or more logic devices along each signal path associated with the target signal input;
• and
• determining the root clock frequency for the logic system design based on a longest signal propagation delay of the signal propagation delays of the plurality of signal paths excluding the target signal path;
• controlling, according to the determined root clock frequency, an emulation process of the logic system design on the emulation system.