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US 11,598,821 B2Granted
Leakage current detection from bias voltage supply of microphone assembly
AssigneeKnowles Electronics, LLC
InventorsTore Sejr Jørgensen, Allan Nielsen
Life of this patent
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Abstract
The present disclosure relates in a first aspect to a method of detecting leakage current from a DC bias voltage circuit of an integrated circuit for a capacitive microelectro mechanical systems (MEMS) transducer. A test signal with a predetermined frequency and level is superimposed on a first DC bias voltage generated by the DC bias voltage circuit.
Claims25
A method of detecting leakage current from a DC bias voltage circuit of an integrated circuit for a capacitive microelectromechanical systems (MEMS) transducer, said method comprising:
- generating a first DC bias voltage by a DC bias voltage circuit,
- lowpass filtering the first DC bias voltage to generate a second DC bias voltage,
- applying the second DC bias voltage to first and second bias voltage pads of the DC bias voltage circuit when the capacitive MEMS transducer, or an equivalent test capacitor, is coupled to the first and second bias voltage pads;
- superimposing a test signal with a predetermined frequency and level onto the first DC bias voltage when the second DC bias voltage is applied to the first and second bias voltage pads;
- detecting a level of the test signal after buffering or amplifying the test signal with a microphone buffer or preamplifier of the integrated circuit coupled to an output of the capacitive MEMS transducer, or through the equivalent test capacitor;
- comparing the test signal to a reference after buffering or amplifying;
- and
- determining whether the integrated circuit failed or passed a leakage current test based on the comparison.
5 more elements
A microphone assembly comprising:
- a housing having a host device interface,
- a capacitive MEMS transducer disposed in the housing, said transducer configured to convert sound into an electrical signal at a transducer output;
- an integrated circuit disposed in the housing and electrically coupled to the host device interface and to the capacitive MEMS transducer via first and second bias voltage pads;
- said integrated circuit further comprising:
- a DC bias voltage circuit configured to generate a first DC bias voltage,
- a test signal generator coupled to the DC bias voltage circuit and configured to generate a test signal with a predetermined frequency and level, wherein the test signal is superimposed onto the first DC bias voltage,
- a lowpass filter coupled between the DC bias voltage circuit and the first bias voltage pad of the integrated circuit, the lowpass filter configured to suppress noise from the first DC bias voltage,
- a buffer or preamplifier circuit comprising an input electrically coupled to the second bias voltage pad;
- wherein the test signal is provided at the host device interface after buffering or amplification.
6 more elements
An integrated circuit for coupling to a capacitive MEMS transducer disposed within a housing of a microphone assembly, the integrated circuit comprising:
- first and second bias voltage pads connectable to electrodes of a capacitive MEMS transducer;
- a DC bias voltage circuit configured to generate a first DC bias voltage;
- a lowpass filter coupled between an output of the DC bias voltage circuit and the first bias voltage pad of the integrated circuit, the lowpass filter configured to suppress noise from the first DC bias voltage,
- a test signal generator coupled to the DC bias voltage circuit and configured to generate a test signal with a predetermined frequency and level, wherein the test signal is superimposed onto the first DC bias voltage;
- a buffer or preamplifier circuit comprising an input electrically coupled to the second bias voltage pad,
- wherein the test signal is buffered or amplified when the second DC bias voltage is applied to first and second bias voltage pads of the integrated circuit in the presence of the capacitive MEMS transducer;
- an analog-to-digital converter (ADC) connected to an output of the buffer or preamplifier circuit and configure to generate a digital test signal by sampling and quantizing the buffered or amplified test signal;
- and
- a data communication interface configured to transmit the digital test signal from the integrated circuit.
6 more elements
Dependencies are inferred from the claim text.