Spiking neural network accelerator using external memory

A neural network accelerator for processing spiking neural network operations, the neural network accelerator comprising:

• neural processing circuitry to process of a plurality of neurons of a neural network with respective neural processor clusters, wherein the neural processing circuitry includes:
• address generation circuitry to determine, based on the received spike message, a corresponding memory address in a memory indicating the synapse data that includes a list of synapses of the presynaptic neuron;
• wherein the the neural processing circuitry is to:
• determine and maintain respective states of the plurality of neurons;
• communicate spike messages within the neural network accelerator, based on the respective states;
• retrieve neuron state data for the particular postsynaptic neuron from the memory, based on the corresponding memory address;
• modify a potential of the particular postsynaptic neuron indicated in the neuron state data, based on the spike message received from the axon processing circuitry;
• and
• write the neuron state data for the particular postsynaptic neuron back to the memory;
• and
• axon processing circuitry to process synapse data of a plurality of synapses in the neural network with respective axon processors, with the circuitry to:
• communicate the spike messages with the neural processing circuitry;
• retrieve synapse data of a subset of the plurality of synapses from a bank of the memory that is external to the neural network accelerator;
• evaluate the synapse data, based on a spike message received from a presynaptic neuron of a neural processor cluster;
• and
• transmit, based on the evaluated synapse data, a weighted spike message to a postsynaptic neuron at a neural processor cluster.

At least one non-transitory machine readable medium including instructions for processing spiking neural network operations, wherein the instructions, when executed, configure neuromorphic processing circuitry to perform operations comprising:

• configuring a plurality of neural processor clusters, each of the neural processor clusters:
• including address generation circuitry to determine, based on the received spike message, a corresponding memory address in an internal memory indicating the synapse data that includes a list of synapses of the presynaptic neuron;
• and
• to operate a plurality of neurons of a neural network, with the neural processor clusters configured to:
• determine and maintain respective states of the plurality of neurons;
• and
• communicate spike messages within the neuromorphic processing circuitry, based on the respective states;
• determine, based on a spike message received from a respective axon processor, a corresponding memory address for a particular postsynaptic neuron tracked in the internal memory of the neuromorphic processing circuitry;
• retrieve neuron state data for the particular postsynaptic neuron from the internal memory, based on the corresponding memory address;
• modify a potential of the particular postsynaptic neuron indicated in the neuron state data, based on the spike message received from the respective axon processor;
• and
• write the neuron state data for the particular postsynaptic neuron back to the internal memory;
• and
• configuring a plurality of axon processors, each of the axon processors being coupled to respective banks of external memory, and each of the axon processors to process synapse data of a plurality of synapses in the neural network, with the axon processors configured to:
• retrieve synapse data of a subset of the plurality of synapses from a bank of memory, the memory being external to the neuromorphic processing circuitry;
• evaluate the synapse data, based on a spike message received from a presynaptic neuron of a neural processor cluster;
• and
• transmit, based on the evaluated synapse data, a weighted spike message to a postsynaptic neuron at a neural processor cluster.