Clock data calibration circuit

A clock data calibration circuit, comprising:

• a first comparator comparing first input data with second input data to generate a data signal;
• a multi-phase clock generator comparing a first input clock and a second input clock to generate a plurality of clock signals with different phases, wherein the plurality of clock signals are divided into a plurality of clock groups;
• a plurality of samplers sampling the data signal according to the plurality of clock groups to, respectively generate a plurality of first sampled data signal groups, wherein each of the plurality of samplers samples the data signal according to one of the plurality of clock groups to generate a corresponding first sampled data signal group;
• a plurality of data comparators, respectively sampling the plurality of first sampled data signal groups according to a plurality of selected clocks in the plurality of clock signals to, respectively, generate a plurality of second sampled data signal groups, wherein each of the data comparators generates a plurality of status flags according to a variation state of a plurality of second sampled data of each of the second sampled data signal groups, wherein each of the plurality of data comparators samples one of the first sampled data signal groups according to one of the plurality of selected clocks;
• and
• a data selector selecting the second sampled data according to the plurality of status flags to generate a plurality of output data signals.