Apparatus and methods for clock duty cycle correction and deskew
AssigneeAnalog Devices, Inc.
InventorWei-Hung Chen
Life of this patent
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Abstract
Apparatus and methods for clock duty cycle correction and deskew are provided. In certain embodiments, a clock distribution circuit includes a clock driver that provides a differential clock signal to a clock slicer over a pair of transmission lines. The clock distribution circuit further includes a resistor-inductor-capacitor (RLC) tuning circuit for providing termination between the pair of transmission lines and a differential input to the clock slicer. The RLC tuning circuit includes a pair of resistor digital-to-analog converters (resistor DACs or RDACs) coupled to the pair of transmission lines and a pair of controllable inductor-capacitor (LC) circuits coupled to the pair of transmission lines.
Claims20
A clock distribution circuit comprising:
- a clock slicer having a differential input;
- a pair of transmission lines including a first transmission line and a second transmission line;
- a clock driver configured to provide a differential clock signal to the differential input of the clock slicer over the pair of transmission lines;
- and
- a resistor-inductor-capacitor (RLC) tuning circuit configured to provide termination to the differential input of the clock slicer, the RLC tuning circuit including a first resistor digital-to-analog converter (RDAC) coupled to the first transmission line, a second RDAC coupled to the second transmission line, a first controllable LC circuit coupled to the first transmission line, and a second controllable LC circuit coupled to the second transmission line.
A method of clock signal distribution, the method comprising:
- providing a differential clock signal to a differential input of a clock slicer over a pair of transmission lines including a first transmission line and a second transmission line;
- providing a duty cycle correction to the differential clock signal at the input of the clock slicer by controlling a first resistor digital-to-analog converter (RDAC) coupled to the first transmission line and a second RDAC coupled to the second transmission line;
- and
- providing a deskew correction to the differential clock signal at the input of the clock slicer by controlling a first controllable LC circuit coupled to the first transmission line and a second controllable LC circuit coupled to the second transmission line.
A semiconductor die comprising:
- a clock distribution circuit comprising:
- a clock slicer having a differential input;
- a pair of transmission lines including a first transmission line and a second transmission line;
- a clock driver configured to provide a differential clock signal to the differential input of the clock slicer over the pair of transmission lines;
- and
- a resistor-inductor-capacitor (RLC) tuning circuit configured to provide termination to the differential input of the clock slicer, the RLC tuning circuit including a first resistor digital-to-analog converter (RDAC) coupled to the first transmission line, a second RDAC coupled to the second transmission line, a first controllable LC circuit coupled to the first transmission line, and a second controllable LC circuit coupled to the second transmission line;
- and
- a core circuit having timing controlled by an output clock signal from the clock slicer.
Dependencies are inferred from the claim text.