A fully-differential two-stage operational amplifier circuit, comprising a first-stage amplification circuit, a second-stage amplification circuit, a common-mode signal acquisition circuit, a common-mode feedback circuit, and a bias circuit;
- wherein
- the first-stage amplification circuit has a cascade structure, and the first-stage amplification circuit receives differential input signals INP and INN;
- the second-stage amplification circuit has a common-source structure, and the second-stage amplification circuit outputs differential output signals OUTP and OUTN;
- the common-mode signal acquisition circuit receives the differential output signals OUTP and OUTN, and outputs an operational amplifier output common-mode signal VCMO;
- the first-stage amplification circuit is connected with the second-stage amplification circuit;
- the common-mode feedback circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a source of the first PMOS transistor and a source of the second PMOS transistor being respectively connected with an external power supply VDD, and a gate of the first PMOS transistor being respectively connected with a drain of the first PMOS transistor and a drain of the first NMOS transistor, a gate of the second PMOS transistor being connected to a drain of the second PMOS transistor and a drain of the second NMOS transistor respectively, a source of the first NMOS transistor being connected to a source of the second NMOS transistor, a gate of the first NMOS transistor receiving an external input reference signal VCM, a gate of the second NMOS transistor receiving the operational amplifier output common-mode signal VCMO, and the drain of the second PMOS transistor and the drain of the first PMOS transistor respectively outputting common-mode feedback signals VB1 and VB2 to the first-stage amplification circuit and the second-stage amplification circuit;
- and
- the bias circuit comprises a resistor R0, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, a positive terminal of the resistor R0 receiving a reference current iref, and the positive terminal of the resistor R0 being connected with a gate of the third NMOS transistor and a gate of the fifth NMOS transistor respectively, a negative terminal of the resistor R0 being connected with a drain of the fifth NMOS transistor, a gate of the sixth NMOS transistor and a gate of the fourth NMOS transistor respectively, a source of the fifth NMOS transistor being connected with a drain of the sixth NMOS transistor, a drain of the third NMOS transistor being connected with the source of the first NMOS transistor and the source of the second NMOS transistor respectively, and a source of the third NMOS transistor being connected with a drain of the fourth NMOS transistor, a source of the fourth NMOS transistor and a source of the sixth NMOS transistor being both grounded, the drain of the third NMOS transistor outputting a bias voltage VB3 to the first-stage amplifier circuit, and the positive and negative terminals of the resistor R0 respectively outputting bias voltages VB4 and VB5 to the first-stage amplifier circuit.