Transmitting data between regions of varying safety integrity levels in a system on a chip
AssigneeNVIDIA Corporation
InventorsMichael Ditty, Hari U. Krishnan, Padam Patt Krishnani, Jyotirmaya Swain, Anirban Ghosh, Shraddha Manohar Gondkar, Avinash J V, Phanikumar Parvatham
Life of this patent
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Abstract
In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.
Claims48
A system comprising:
- a memory operating in compliance with a first risk classification level;
- and
- circuitry operating in compliance with a second risk classification level that indicates a higher risk classification than the first risk classification level, the circuitry to determine an error detection code for data to be written to a first memory address within the memory, determine a second memory address within the memory based at least in part on the first memory address, and cause the data to be stored in the first memory address and the error detection code to be stored in the second memory address.
A system comprising:
- a memory to operate within a first risk classification level, the memory comprising an isolated memory region comprising a first memory address storing data and a second memory address storing an error detection code;
- and
- circuitry to operate within a second risk classification level that indicates a higher level of risk than the first risk classification level, the circuitry to obtain the data from the first memory address, obtain the error detection code from the second memory address, and generate a notification when the error detection code indicates the data contains at least one error.
A method performed by circuitry operating at a first risk classification level, the method comprising:
- determining an error detection code for data to be written to a first memory address within a memory operating at a second risk classification level that indicates a lower level of risk than the first risk classification level;
- determining a second memory address within the memory based at least in part on the first memory address;
- and
- causing the data to be stored in the first memory address and the error detection code to be stored in the second memory address.
A method performed by circuitry operating at a first risk classification level, the method comprising:
- obtaining data from a first memory address of a memory operating at a second risk classification level that indicates a lower level of risk than the first risk classification level;
- determining a second memory address within the memory based at least in part on the first memory address;
- obtaining an error detection code from the second memory address;
- and
- generating a notification when the error detection code indicates the data contains at least one error.
Dependencies are inferred from the claim text.