US 11,569,828 B2Granted

Current operative analog to digital converter (ADC)

AssigneeSigmasense, LLC.

InventorPhuong Huynh

Life of this patent

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Abstract

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).

Claims20

Dependent claims

An analog to digital converter (ADC) comprising:

an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to an input of the operational amplifier and to an output of the operational amplifier, wherein the input of the operational amplifier is coupled to the load via a single line;
an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and configured to:
receive the load voltage;
receive a reference voltage;
and
compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;
memory that stores operational instructions;
one or more processing modules operably coupled to the M-bit ADC and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal;
and
an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules, wherein, when enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal, the DAC output current tracks the load current, and the load voltage tracks the reference voltage, wherein:
N is a first positive integer;
M is a second positive integer greater than or equal to 1;
and
N is greater than M.

11 more elements

An analog to digital converter (ADC) comprising:

an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to a first input of the operational amplifier and to an output of the operational amplifier, wherein a second input of the operational amplifier is grounded, wherein the first input of the operational amplifier is coupled to the load via a single line;
an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and configured to:
receive the load voltage;
receive a reference voltage;
and
compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;
memory that stores operational instructions;
one or more processing modules operably coupled to the M-bit ADC and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to:
process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal;
and
process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the load voltage;
and
an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules, wherein, when enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal, the DAC output current tracks the load current, and the load voltage tracks the reference voltage, wherein:
N is a first positive integer;
M is a second positive integer greater than or equal to 1;
and
N is greater than M.

14 more elements

An analog to digital converter (ADC) comprising:

an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to a first input of the operational amplifier and to an output of the operational amplifier, wherein a second input of the operational amplifier is grounded, wherein the first input of the operational amplifier is coupled to the load via a single line;
an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and configured to:
receive the load voltage;
receive a reference voltage;
and
compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;
memory that stores operational instructions;
one or more processing modules operably coupled to the M-bit ADC and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal;
and
an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules, wherein, when enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal, the DAC output current tracks the load current, and the load voltage tracks the reference voltage, wherein:
N is a first positive integer;
M is a second positive integer greater than or equal to 1;
N is greater than M;
and
the ADC further configured to provide power to the load and simultaneously sense the load voltage.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/503,435Filed 18 Oct 2021 · continuation
Priority: 8 Nov 2019
Published: US 2022/0038109 A13 Feb 2022
Granted: 31 Jan 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03M 1/0626
Characterised by the use of methods or means not specific to a particular type of detrimental influence: by filtering
H03M 1/1245
Sampling or signal conditioning arrangements specially adapted for A/D converters: details of sampling arrangements or methods
H03M 1/462
With digital/analogue converter for supplying reference values to converter: details of the control circuitry, e.g. of the successive…
H03M 1/464
With digital/analogue converter for supplying reference values to converter: non-linear conversion

Family

Application16/678,793Parent of this continuation · filed 8 Nov 2019
Application17/083,463Parent of this continuation · filed 29 Oct 2020
US 10,862,492 B1Parent of this continuation · filed 8 Dec 2020
US 2022/0038109 A1Pre-grant publication · published 3 Feb 2022
US 11,152,948 B2Parent of this continuation
US 2021/0143829 A1Published application
US 11,569,828 B2This patent

From the US filing history. Foreign family members aren’t listed.