Apparatus, systems, and methods for providing computational imaging pipeline
AssigneeMovidius Limited
InventorsDavid Moloney, Cormac Brick, Ovidiu Andrei Vesa, Brendan Barry
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Abstract
The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
Claims15
A parallel processing device, the parallel processing device comprising:
- first processing circuits and second processing circuits, the first and second processing circuits to issue memory requests;
- a memory slice including random access memory (RAM) tiles, the RAM tiles having individual read and write ports;
- an interconnect system structured to couple the first and second processing circuits;
- a first clash detector communicatively connected to the first processing circuits to detect a first memory request to a first one of the RAM tiles;
- a second clash detector communicatively connected to the second processing circuits to detect a second memory request to the first one of the RAM tiles, the first and second clash detectors to detect the first and second memory requests to the first one of the RAM tiles in parallel;
- and
- an arbitration block to generate a halt signal when the first and second processing circuits issue respective ones of the first and second memory requests to the one of the RAM tiles, the halt signal to block one of the first or second processing circuits from completing a memory operation.
A method for operating a parallel processing system, the method comprising:
- coupling first processing circuits and second processing circuits with a memory slice, the memory slice including random access memory (RAM) tiles having individual read and write ports, the first and second processing circuits structured to execute instructions;
- detecting, by a first clash detector communicatively connected to the first processing circuits, a first memory access request to a first one of the RAM tiles;
- detecting, by a second clash detector communicatively connected to the second processing circuits, a second memory access request to the first one of the RAM tiles, the first and second clash detectors detecting the first and second memory access requests to the first one of the RAM tiles in parallel;
- and
- sending, by an arbitration block, a first authorization message to one of the first or second processing circuits to authorize access to the first one of the RAM tiles.
Dependencies are inferred from the claim text.