Wafer-level package structure

The wafer-level packaging structure, comprising:

• a device wafer;
• a plurality of first chips, bonded to the device wafer, wherein the first chip of the plurality of first chips includes a chip front surface with a formed first pad and a chip back surface opposite to the chip front surface, and the chip front surface faces the device wafer;
• a first encapsulation layer, formed on the device wafer and covering the first chips, wherein the first encapsulation layer has a first opening exposing at least one first chip of the plurality of first chips and the chip back surface exposed by the first opening is connected to a loading signal;
• a metal layer structure, covering the at least one first chip exposed by the first opening, a bottom and sidewalls of the first opening and a top of the first encapsulation layer, wherein the metal layer structure includes a back metal layer alloyed with the chip back surface by an alloying treatment between the chip back surface and a portion of the metal layer structure on the chip back surface;
• and
• a second encapsulation layer, formed in the first opening, covering the back metal layer, and further covering the metal layer structure on the top of the first encapsulation layer.