Scalable runtime validation for on-device design rule checks

A method comprising:

• receiving, by a validator of a hardware accelerator device, design rule information for one or more multiplexers of the hardware accelerator device, the design rule information referencing a contention set stored in memory of the hardware accelerator device, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the one or more multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the one or more multiplexers and comprises information identifying where routing intellectual properties (IPs) are located on each row of the hardware accelerator device, identifying frames and frames bits configured for each of the one or more multiplexers in the routing IPs, and configuration rules;
• receiving, at the validator of the hardware accelerator device, the user bitstream for programming the one or more multiplexers of the hardware accelerator device;
• analyzing, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the hardware accelerator device;
• and
• providing, by the validator, an error indication responsive to identifying a match between the user bitstream and the contention set.

A non-transitory machine readable storage medium comprising instructions that, when executed, cause at least one processor to at least:

• receiving, by a validator of a hardware accelerator device, design rule information for one or more multiplexers of the hardware accelerator device, the design rule information referencing a contention set stored in memory of the hardware accelerator device, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the one or more multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the one or more multiplexers and comprises information identifying where routing intellectual properties (IPs) are located on each row of the hardware accelerator device, identifying frames and frames bits configured for each of the one or more multiplexers in the routing IPs, and configuration rules;
• receiving, at the validator of the hardware accelerator device, the user bitstream for programming the one or more multiplexers of the hardware accelerator device;
• analyzing, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the hardware accelerator device;
• and
• providing, by the validator, an error indication responsive to identifying a match between the user bitstream and the contention set.